Browse Prior Art Database

Memory Decode Architecture

IP.com Disclosure Number: IPCOM000043647D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Davis, TH: AUTHOR [+2]

Abstract

Memory decode architecture is described for data processing systems having pipelined addressing bus cycles, such as the Intel 80286 processor, which maximizes the cycle time performance of memory or I/O. The timing of the address outputs is pipelined from the bus interface unit of the Intel 80286 processor chip. This allows as much time as possible for the data access. The timing of the address outputs is pipelined such that the address of the next bus operation becomes available during the current bus operation. Address decode and routing logic can operate in advance of the next bus operation. As shown in the figure, the local address signals LA17 through LA23 were added to the I/O channel, to take advantage of the pipelined addressing of the Intel 80286 for memory address.

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Memory Decode Architecture

Memory decode architecture is described for data processing systems having pipelined addressing bus cycles, such as the Intel 80286 processor, which maximizes the cycle time performance of memory or I/O. The timing of the address outputs is pipelined from the bus interface unit of the Intel 80286 processor chip. This allows as much time as possible for the data access. The timing of the address outputs is pipelined such that the address of the next bus operation becomes available during the current bus operation. Address decode and routing logic can operate in advance of the next bus operation. As shown in the figure, the local address signals LA17 through LA23 were added to the I/O channel, to take advantage of the pipelined addressing of the Intel 80286 for memory address. The figure shows decoding of the local address bus using a PROM (programmable read-only memory) and a latch. Because of the limited number of local address lines available on the I/O channel, 128K-byte boundaries are the minimum decode size. External address latches are used on the system address lines (not shown) to hold the address stable for the entire bus operation. The local address lines are buffered, but not latched. Each memory device wishing to take advantage of the increased decode time must decode its chip select from LA17-LA23 and latch the chip select data on the falling edge of address latch enable (ALE). A transparent latch, as shown in the figure, is...