Browse Prior Art Database

Low Cost Multi-Chip Package

IP.com Disclosure Number: IPCOM000043676D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Hubacher, EM: AUTHOR

Abstract

This multi-chip package is aimed at achieving low cost, flexibility, and quick turnaround. The package, primarily designed for low end users, allows for 8 or 9 chips on a substrate, but is extendable to more chips in one package. The package is made up of two parts, i.e., a base multilevel ceramic substrate 10 which is a stock part, and one or more layers 12 (Fig. 1) on the surface of substrate 10 which provide the interconnections for the chips and personality wiring needed for a particular application. The substrate 10 contains brazed pins and filled vias to bring both power and signal I/O's up through various layers in the ceramic. Power planes embedded within the structure are used to distribute power to the chips on the surface. Connecting vias 33 (Fig. 2) bring the power to the surface away from the chip footprint area.

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Low Cost Multi-Chip Package

This multi-chip package is aimed at achieving low cost, flexibility, and quick turnaround. The package, primarily designed for low end users, allows for 8 or 9 chips on a substrate, but is extendable to more chips in one package. The package is made up of two parts, i.e., a base multilevel ceramic substrate 10 which is a stock part, and one or more layers 12 (Fig. 1) on the surface of substrate 10 which provide the interconnections for the chips and personality wiring needed for a particular application. The substrate 10 contains brazed pins and filled vias to bring both power and signal I/O's up through various layers in the ceramic. Power planes embedded within the structure are used to distribute power to the chips on the surface. Connecting vias 33 (Fig. 2) bring the power to the surface away from the chip footprint area. This permits connection of various C4 power configurations to the power vias via MC (metallized ceramic) or any thick film technology used to form layer 12. To provide a quick turnaround, a ceramic substrate with the previously defined internal structure and wiring is proposed. This is a stock ceramic base substrate that can be built and stocked for later use. The off-the-shelf feature circumvents the problem of lead time as well as cost associated with the normal MLC (multilayer ceramic) substrates by not having to build all the masks, punch tapes, test tapes, inspection data, etc., for each part number. A total of 5 to 10 layers are provided to handle the requirements of the substrate, such as providing power distribution, redistribution of the signal layers, and providing a path from the top surface to the bottom I/O pads. The top surface of the substrate contains molybdenum or tungsten-filled via holes which are picked up by top surface MC or thick film wiring. The bottom surface contains circular MLC-type pads. The bottom surface could also contain a set of via holes for bottom side wiring. Between the chip frames the bottom surface contains circular MLC-type pads. The bottom surface could also contain a set of via holes for bottom side wiring. Between the chip frames 14 are provided two rows of vias. The vias 16 in the row furthest from the edge of the substrates are connected to a set of internal subways running from one side of the substrate to the other. This fixed wiring is used to facilitate the interconnection of chips. Towards the edge of the substrate and next to the row of subway vias 16 is a second row of vias 18 that connect internally to the bottom pads of the substrate. These vias are used to connect internally to the bottom pads of the substrate. Located along the edge of the inner chip frame is another set of vias...