Browse Prior Art Database

Single I/O Balanced Driver

IP.com Disclosure Number: IPCOM000043678D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Chang, AY: AUTHOR [+4]

Abstract

A balanced input-output (I/O) driver is disclosed wherein current flow through pin inductances remains unchanged despite signal level transients. One of the problems of high speed communication between chips in a multiple-chip module environment or module-to-module communication environment is the so-called WI noise. The WI noise arises from the inductive voltage drop on the module power pin due to the surging current of the driver. Such noise will not only disturb non-switching circuits but will also slow down the rise time of the switching driver. These problems are addressed by the single I/O balanced driver. As shown in the figures, the driver consists of three transistors. The three transistors form a current switch configuration. Transistor 3 is the current source.

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Single I/O Balanced Driver

A balanced input-output (I/O) driver is disclosed wherein current flow through pin inductances remains unchanged despite signal level transients. One of the problems of high speed communication between chips in a multiple-chip module environment or module-to-module communication environment is the so-called WI noise. The WI noise arises from the inductive voltage drop on the module power pin due to the surging current of the driver. Such noise will not only disturb non-switching circuits but will also slow down the rise time of the switching driver. These problems are addressed by the single I/O balanced driver. As shown in the figures, the driver consists of three transistors. The three transistors form a current switch configuration. Transistor 3 is the current source. The collector of transistor 1 acts as the I/O terminal. A signal line connects the I/O and the terminator R which is terminated by the VCC supply. The signal line runs between VCC meshes inside the module. The collector of transistor 2 is connected to the VCC supply on the chip power bus. Fig. 1 shows the current flow path for the up-level steady-state condition. Current I flows from VCC through the receiver side pin inductance LR into the VCC meshes 1 and 2, then to driver transistor 2, current source transistor 3, LD, the driver side pin inductance, and, finally, to the VEE power bus. LR and LD are the primary inductances which cause the WI noise. Current flow for the...