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Interrupt Dispatching Method for Multiprocessing System

IP.com Disclosure Number: IPCOM000043680D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Giroir, D: AUTHOR [+4]

Abstract

The interrupt dispatching method is to be used in a multiprocessor system for passing control between components: processors and input/ output adapters. The pool of processors handles the interrupt requests originating from the pool of adapters and/or the pool of processors itself. Hence, any of the I/O adapters and/or the processors may pass control to any of the processors with no predefined scheme of allocation. The system status is recorded in a Directory which reflects the availability of processing resources: one entry per processor is defined, each entry holding the processor status for its interrupt level (or levels when more than one). The Directory is under direct control of an interrupt dispatcher which provides the processor selection within the pool on behalf of the I/O adapters or the requesting processor.

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Interrupt Dispatching Method for Multiprocessing System

The interrupt dispatching method is to be used in a multiprocessor system for passing control between components: processors and input/ output adapters. The pool of processors handles the interrupt requests originating from the pool of adapters and/or the pool of processors itself. Hence, any of the I/O adapters and/or the processors may pass control to any of the processors with no predefined scheme of allocation. The system status is recorded in a Directory which reflects the availability of processing resources: one entry per processor is defined, each entry holding the processor status for its interrupt level (or levels when more than one). The Directory is under direct control of an interrupt dispatcher which provides the processor selection within the pool on behalf of the I/O adapters or the requesting processor. The dispatcher updates the Directory accordingly. The Directory may also modify its contents upon request, to reflect the current operating processor configuration. The Directory also reflects the processor availability at the task completion. The processor allocation for an interrupt required is performed according to two criteria, namely, the eligibility criterion, and the ordering criterion. A processor is eligible to handle an interrupt request if its corresponding interrupt level is not already active. "Active" means that some work has been initiated and has not yet been terminated on this interrupt level. Two subsets of eligible processors are defined: 1) Fully available processors: those which are busy on a lowest priority level than the requested one. If allocated,

the interrupt will stop the current work on such processors.
2) Partially available processors: those which are busy

on a higher priority level than the requested one, but are

available on this requested level. This may be due to

effective execution on the higher level of interruption but

also to unavailability for masking reasons (e.g., that

processor has not this level of priority processing

responsibility). The partially available processor subset is used by the selection algorithm only when the fully available processor subset is empty, i.e., when all processors are busy on a higher priority level than the requested one. When both subsets are empty, the interrupt request is postponed until one processor terminates its job on the requested level. In order to balance the processing load over the pool of processors, the selection is achieved according to a round-robin scheme: the processors are chained together. The choice of the processor is performed from a starting point in the chain. The starting point is updated according to an algorithm which equally distributes the probability of selection among the chain. For instance, the starting point could be the processor following the last chosen one: if the next processor in the chain is eligible, it will be considered; otherwise, the subsequ...