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Latch Oscillator

IP.com Disclosure Number: IPCOM000043690D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Pollmann, K: AUTHOR [+4]

Abstract

The stage delay of latches can be determined by the circuit of Fig. 1. This circuit is a ring oscillator built from the latches 1 to n and the logic circuits CD1, CS1 to CDn, CSn, INV1. The oscillator frequency depends on the number of stages in the loop. The contribution of the latches to this frequency is determined by comparison with a reference oscillator containing all the stages of the oscillator loop except for the latches. The frequency shift related to the latches is easily converted into the stage delay. The latch ring oscillator oscillates only if the loop includes a clock shaper CS, the circuit diagram of which is shown as an example in Fig. 3. The output of CS is amplified by a clock driver CD consisting of two inverters (Fig. 2). As shown in Fig.

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Latch Oscillator

The stage delay of latches can be determined by the circuit of Fig. 1. This circuit is a ring oscillator built from the latches 1 to n and the logic circuits CD1, CS1 to CDn, CSn, INV1. The oscillator frequency depends on the number of stages in the loop. The contribution of the latches to this frequency is determined by comparison with a reference oscillator containing all the stages of the oscillator loop except for the latches. The frequency shift related to the latches is easily converted into the stage delay. The latch ring oscillator oscillates only if the loop includes a clock shaper CS, the circuit diagram of which is shown as an example in Fig. 3. The output of CS is amplified by a clock driver CD consisting of two inverters (Fig. 2). As shown in Fig. 1, the inverting output -L of each latch is connected to the data input of the subsequent latch. To achieve oscillations, the inverting output -L of latch n must be fed back to the data input of latch q. In addition, the number of latches used must be odd, so that the output signal of the last latch is fed back in an inverted form to the first latch. If the ring oscillator is to consist of an even number of latches, an inverter (such as INV1) must be inserted between the inverting output -L of latch n and the data input of latch 1. Through clock shaper CSn, the non-inverting output 0L of latch n is connected to input A01 of clock driver CD1 for latch 1 (Fig. 1). Clock shaper CS, designed ac...