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Double-Boosted Clock-Driver That Exhibits Minimal Creep and Low Input Capacitance Without High Voltage Breakdowns

IP.com Disclosure Number: IPCOM000043707D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+3]

Abstract

The double-boosted clock-driver with minimal creep and low input capacitance is illustrated in the figure. It operates in three phases: 1) Restore Phase (PHRES) PHRES is an input signal that rises to a VH level and returns low. During this phase, nodes N2, N7, and N9 are precharged to a VH-Vt level. Also, since devices T4 and T9 are depletion-mode devices, nodes N3 and N6 charge up to a full VH level. This is an advantage since capacitor C1 is charged up to a full VH level before PHIN rises. As PHRES falls, nodes N2, N7 and N9 are isolated with VH-Vt on them. 2) Precharge Phase (PHIN) PHIN is an input signal that rises (from a preceding clock, for example) then falls with or before the rise of PHRES.

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Double-Boosted Clock-Driver That Exhibits Minimal Creep and Low Input Capacitance Without High Voltage Breakdowns

The double-boosted clock-driver with minimal creep and low input capacitance is illustrated in the figure. It operates in three phases: 1) Restore Phase (PHRES) PHRES is an input signal that rises to a VH level

and returns low. During this phase, nodes N2, N7,

and N9 are precharged to a VH-Vt level. Also,

since devices T4 and T9 are depletion-mode

devices, nodes N3 and N6 charge up to a full VH

level. This is an advantage since capacitor C1 is

charged up to a full VH level before PHIN rises.

As PHRES falls, nodes N2, N7 and N9 are isolated

with VH-Vt on them. 2) Precharge Phase (PHIN)

PHIN is an input signal that rises (from a

preceding clock, for example) then falls with or

before the rise of PHRES. As PHIN rises, T2

self-bootstraps and places PHIN on the gate of T10

and precharges capacitor C3. Since node N4 is

held low by T11 and T11A, T10 turns on (in

saturation). T9 is also on and is large enough so

that most of the current needed by T10 is supplied

by T9, maintaining the charge on capacitor C1.

The capacitive load as seen by PHIN is limited to

the parasitics on N1, the gate of T10, capacitor

C3 (which only needs to be big enough to insure

that T10 is always linear during the next phase),

and the gate of T16. 3) Trigger Phase (PHTRIG)

PHTRIG is an input signal that rises some delayed

amount of time after PHIN rises when PHIN has

reached 70-90% (a Schmitt trigger could be used)

and falls with the fall of PHIN. As PHTRIG

reaches a Vt above ground, T11's gate begins

falling until T11 turns off, such that node N4 can

begin to rise. As it does, node N1 rises through

capacitor C3, keeping device T10 linear. T12 and

T14 t...