Browse Prior Art Database

Multiple Level-Two Caches

IP.com Disclosure Number: IPCOM000043720D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

So, K: AUTHOR

Abstract

A scheme is provided for a multiprocessor (MP) system that reduces cross interrogate (XI) traffic without sacrificing the design and performance of a single level-two cache (L2). The scheme assumes that there are multiple L2's in the MP system. Each L2 is serving one or more CPUs and each CPU has a level-one cache (L1). The memory units in L1 and L2 are lines and blocks, respectively, as shown in the diagram. Each A line in an L2 block is given an additional bit, say, E-bit, to indicate whether the A line is currently in the L2 block or not. If an L2 miss does not result in a XI, bring in the whole L2 block and turn on all E-bits.

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Multiple Level-Two Caches

A scheme is provided for a multiprocessor (MP) system that reduces cross interrogate (XI) traffic without sacrificing the design and performance of a single level-two cache (L2). The scheme assumes that there are multiple L2's in the MP system. Each L2 is serving one or more CPUs and each CPU has a level-one cache (L1). The memory units in L1 and L2 are lines and blocks, respectively, as shown in the diagram. Each A line in an L2 block is given an additional bit, say, E-bit, to indicate whether the A line is currently in the L2 block or not. If an L2 miss does not result in a XI, bring in the whole L2 block and turn on all E-bits. Otherwise, only the A line involved in XI is transferred from the XI'ed L2 to the local L2 with the following actions: o In the XI'ed L2, turn off the E-bit of the XI'ed A line in the XI'ed L2 block. If all the E-bits are

off, delete the L2 block from the XI'ed L2. o Load the XI'ed A line to the local L2. o Add the L2 block to the directory of the local L2 if it is not there. o Turn on the E-bit of the XI'ed A line in the L2 block.

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