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Browse Prior Art Database

High-Speed Chip Card Reading

IP.com Disclosure Number: IPCOM000043724D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Proebster, WE: AUTHOR [+2]

Abstract

Present communication schemes between known chip cards and their terminals require a terminal command or special code for reading bits or bytes from or for writing them into those cards. For normal transactions, involving many bits or bytes, this procedure has to be repeated, which is very time-consuming, particularly if all chip card data have to be read out by banks for final record purposes. This is a regularly recurring operation that may take seconds. To avoid the above-described disadvantage, it is proposed to render the card chips more intelligent. For reading the entire card memory, one terminal command (e.g., "DUMP") should be sufficient for transmitting the entire chip storage contents bit-by-bit to the card terminal. The figure shows the proposed arrangement of the storage part of the chip.

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High-Speed Chip Card Reading

Present communication schemes between known chip cards and their terminals require a terminal command or special code for reading bits or bytes from or for writing them into those cards. For normal transactions, involving many bits or bytes, this procedure has to be repeated, which is very time-consuming, particularly if all chip card data have to be read out by banks for final record purposes. This is a regularly recurring operation that may take seconds. To avoid the above-described disadvantage, it is proposed to render the card chips more intelligent. For reading the entire card memory, one terminal command (e.g., "DUMP") should be sufficient for transmitting the entire chip storage contents bit-by-bit to the card terminal. The figure shows the proposed arrangement of the storage part of the chip. It comprises a standard storage cell array with new peripheral circuitry. The peripherals consist of input latches for storing the address signals for standard selection. The true and complement outputs are fed to the decoder inputs. The decoder output, which is generally fed to the word or bit line driver, is connected to the input of a special gate. A special shift register chain, comprising as many stages as there are word or bit lines, is added to the respective decoders. The output of each register is the second input of the gate. The gate has two functions. The first function, relating to the logic part, is to distinguish between standard array selection (register output = "0") and DUMP operations (register output = "1"). The "1" state at the gate input is always dominant (see truth table). The second function relates to the word or bit line driver part. Operating Modes 1.

Standard array selection o Address signals are fed to word/bit input latches.

(The latches may also be implemented as

standard phase splitter circuits.) o The register is loaded with "0" states. For this purpose, the decoder output

determines the word/bit line state

directly through the gate. The DUMP

switch signal is "off". o Array cells are selected. 2. Total storage array read-out (DUMP) o The DUMP command turns the DUMP switch signal "on"; i.e., all decoder outputs

are "0". The DUMP command generates a

"1" which is fed to the register chain.

The "1" at the gate input always

dominates, overruling the normal address

input. By shifting the "1" through the

chain by means of the clock pulses, all

word lines are selected one after the

other. In this case, word line (WL) or

bit line (BL) selection is solely

dependent on the status of the shift

register. o There are two possibilities of

1

Page 2 of 3

reading

out data:

a) All bits are read in parallel. In

this case, only the word lines have

to be selected through the shift

register. The bit lines are

invariably selected. They feed

either the chip contacts or a

h...