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Scalable CMOS Technology With Enhanced Protection Against Latch-Up

IP.com Disclosure Number: IPCOM000043726D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Lo, TC: AUTHOR

Abstract

The disclosed CMOS (complementary metal oxide semiconductor) structure uses the known processing techniques of fully recessed field oxide isolation (or trench isolation) and retrograde P-well implantation. The arrangement has the advantages of being easily scalable to finer lithography, offers enhanced protection against latch-up, and has the same easiness for LDD (lightly doped drain) inclusion as the conventional CMOS process. Figs. 1-5 show the invention process. The fully recessed field oxide of Fig. 1 improves scalability because it is bird's-beak free, acts to eliminate narrow-W effects due to field implant encroachment as is the case in conventional LOCOS (localized oxidation of silicon), and offers a surface that is more planar.

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Scalable CMOS Technology With Enhanced Protection Against Latch-Up

The disclosed CMOS (complementary metal oxide semiconductor) structure uses the known processing techniques of fully recessed field oxide isolation (or trench isolation) and retrograde P-well implantation. The arrangement has the advantages of being easily scalable to finer lithography, offers enhanced protection against latch-up, and has the same easiness for LDD (lightly doped drain) inclusion as the conventional CMOS process. Figs. 1-5 show the invention process. The fully recessed field oxide of Fig. 1 improves scalability because it is bird's-beak free, acts to eliminate narrow-W effects due to field implant encroachment as is the case in conventional LOCOS (localized oxidation of silicon), and offers a surface that is more planar. The fully recessed field oxide improves latch-up prevention because it significantly reduces the beta of the lateral bipolar transistor directly from silicon surface engraving. It is formed by first engraving the trenches, channel stop implant and then filling trenches with oxide. The retrograde P-well of Fig. 2, implanted with boron, improves scalability because of the shallower well, far less lateral diffusion and good VT control at no compromise of good P-well conductivity. In this regard, the retrograde P-well improves latch-up protection because it reduces dramatically the beta of the vertical NPN transistor due to retarding field in its base. Also, the high c...