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High Performance 64-Bit DCCS Adder

IP.com Disclosure Number: IPCOM000043727D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

A high speed 64-bit full adder is described that is implemented in 5 high Differential Cascode Current Switching (DCCS) circuits with a maximum of 6 stages of delay and a carry out in 4 stages of delay. A high speed full adder is useful for floating point and scientific computations. In many instances, add-type instructions comprise over 50% of the floating point instructions executed and full adders may also be utilized in Multiply and Divide. Depending upon the circuit design and bipolar technology chosen, DCCS trees may exhibit delays of .5 ns to 2 ns. A 64-bit full adder is described here that has a maximum of 6 stages of delay to generate all sums and 4 stages of delay to generate the carry out, giving an add time of 3 to 12 ns.

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High Performance 64-Bit DCCS Adder

A high speed 64-bit full adder is described that is implemented in 5 high Differential Cascode Current Switching (DCCS) circuits with a maximum of 6 stages of delay and a carry out in 4 stages of delay. A high speed full adder is useful for floating point and scientific computations. In many instances, add-type instructions comprise over 50% of the floating point instructions executed and full adders may also be utilized in Multiply and Divide. Depending upon the circuit design and bipolar technology chosen, DCCS trees may exhibit delays of .5 ns to 2 ns. A 64-bit full adder is described here that has a maximum of 6 stages of delay to generate all sums and 4 stages of delay to generate the carry out, giving an add time of 3 to 12 ns. Since the carry out is generated in 4 stages of delay, it follows that any other internal carry could also be generated in 4 stages of delay and therefore all sums could be generated with 5 stages of delay. The adder described is a compromise between the number of circuits used and the addition of 1 additional stage of delay. Representative circuits are shown in Figs. 1-9. A breakdown of the circuits is as follows: 2-bit carry and propagate functions - 64 circuits

64 sums - 64 circuits

Carry out - 1 circuit

Look ahead - 24 circuits

Functions required

for sums - 29 circuits

TOTAL 182 circuits This circuit count does not include translators which are required for current switch circuits but not requir...