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Browse Prior Art Database

Non-Overlap Clock Generation Circuit

IP.com Disclosure Number: IPCOM000043729D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Cases, M: AUTHOR [+3]

Abstract

A clock generation circuit is described which generates two non-overlapping output clock signals from a single input clock signal. The non-overlapping clock generator circuit is shown in Fig. 1 wherein the input clock signal produces the two non-overlapping clock output signals B and C. Fig. 2 shows the input signal waveform A and the resulting non-overlapping output waveforms B and C. The non-overlapping action of this circuit is mainly provided by transistors 7 and 8. Initially, when input A is positive, output B is kept negative by either transistor 4 or 7 which is ON. Output C is kept positive when both transistors 6 and 8 are OFF. As input A begins to change from positive to negative, transistor 4 turns OFF, having no effect on output B since transistor 7 is still turned ON by output C.

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Non-Overlap Clock Generation Circuit

A clock generation circuit is described which generates two non-overlapping output clock signals from a single input clock signal. The non-overlapping clock generator circuit is shown in Fig. 1 wherein the input clock signal produces the two non-overlapping clock output signals B and C. Fig. 2 shows the input signal waveform A and the resulting non-overlapping output waveforms B and C. The non-overlapping action of this circuit is mainly provided by transistors 7 and 8. Initially, when input A is positive, output B is kept negative by either transistor 4 or 7 which is ON. Output C is kept positive when both transistors 6 and 8 are OFF. As input A begins to change from positive to negative, transistor 4 turns OFF, having no effect on output B since transistor 7 is still turned ON by output
C. Once transistor 2 turns OFF, transistor 6 begins turning ON, pulling down output C, which in turn shuts OFF transistor 7, allowing output B to rise since transistor 4 is now turned OFF by input A. Fig. 3 shows how the circuit may be modified to provide improved driving capability at the same power level.

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