Browse Prior Art Database

Error Correction for Block Transfer Storage

IP.com Disclosure Number: IPCOM000043730D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Ryan, PM: AUTHOR

Abstract

Block transfer memory systems, because of their size (109-1010 bytes), pose a particular problem in the correction of multiple errors. Such memories are organized to provide several thousand bytes of data in consecutive words from consecutive cells of one or more error correcting code (ECC)-related array chips for each request for a block transfer. Individual faults occurring from time to time in the array chips can cause errors in the stream of ECC words in some of the blocks. As long as no word contains more errors than can be corrected in-line by the ECC logic, each block transfer is correctly completed in one pass through the sequence of consecutive addresses.

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Error Correction for Block Transfer Storage

Block transfer memory systems, because of their size (109-1010 bytes), pose a particular problem in the correction of multiple errors. Such memories are organized to provide several thousand bytes of data in consecutive words from consecutive cells of one or more error correcting code (ECC)-related array chips for each request for a block transfer. Individual faults occurring from time to time in the array chips can cause errors in the stream of ECC words in some of the blocks. As long as no word contains more errors than can be corrected in-line by the ECC logic, each block transfer is correctly completed in one pass through the sequence of consecutive addresses. When two or more faults align, however, to produce more errors in one or more words than can be corrected by ECC, an uncorrectable error (UE) results and further action is necessary to recover the correct data. One technique for doing this is the complement/recomplement block-oriented method which requires one initial and three subsequent transfers to correct several multiple-error words in a block. The technique for error correction for block transfer storage disclosed in this article is superior to the complement/recomplement technique, being faster (requiring less memory cycles) and achieving a more efficient level of recovery. It is based upon design of an optimized block transfer storage structure, one which forces the vast majority of faults causing multiple uncorrectable errors to identify themselves upon a first transfer of data, and to be corrected upon one subsequent transfer rather than depending upon three subsequent transfers as does the complement/recomplement technique. Fig. 1 shows a high level diagram of hardware for implementing more efficient recovery. The Multiplex (MUX) Box multiplexes among two or more groups of ECC-related chips, only the shift register and the Worst-Bit Detector needing to be replicated and multiplexed in sync with the multiplexing between the two chip groups. If chip access time and transfer rate are well-matched, only one ECC-related group of array chips may be involved in a block transfer and the MUX may be omitted. The Pre-Correct Box is inactive during the first pass access to any block, and data passes through it unaltered. The ECC Detect and Correct Box is conventional, generating a syndrome for each word transferred in the block. This syndrome identifies the positions of correctable errors fo...