Browse Prior Art Database

Microprocessor-Controlled Programmable Event Timer

IP.com Disclosure Number: IPCOM000043731D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Hall, AE: AUTHOR [+2]

Abstract

A technique is described whereby event timing control hardware is incorporated along with a microprocessor to relieve the microprocessor of trivial tasks, such as applications where certain events must be kept active or inactive for multiple clock frequency periods, or in applications where an event is repeated for long periods of time. By incorporating event timing control hardware, the microprocessor is not required to continuously monitor the status of the events. The event timing control hardware utilizes readily available computer components, such as a 74191 counter and a pair of 7485 magnitude comparators. Magnitude comparators 1 and 2 receive information at inputs A from the microprocessor (MPU).

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Microprocessor-Controlled Programmable Event Timer

A technique is described whereby event timing control hardware is incorporated along with a microprocessor to relieve the microprocessor of trivial tasks, such as applications where certain events must be kept active or inactive for multiple clock frequency periods, or in applications where an event is repeated for long periods of time. By incorporating event timing control hardware, the microprocessor is not required to continuously monitor the status of the events. The event timing control hardware utilizes readily available computer components, such as a 74191 counter and a pair of 7485 magnitude comparators. Magnitude comparators 1 and 2 receive information at inputs A from the microprocessor (MPU). Comparator 1 represents the number of times the event is in an "on" state and comparator 2 represents the number of times the event is in an "off" state. Inputs B of comparators 1 and 2 are fed from the counter 3 through AND gates 4 and 7, respectively. The microprocessor initiates the event sequence by enabling the counter 3 and setting flip-flop 5 (FF2). Counter 3 starts counting, supplying signals to inputs B of comparator 1 through AND gates 4. The inputs B to comparator 2 are disabled. When the counter count equals the A inputs of comparator 1, the output A = B of comparator 1 becomes active. Flip-flop 6 (FF1) is now set. Counter 3 and flip-flop 5 (FF2) are now cleared. The setting of flip-flop 6 (FF1) enable...