Browse Prior Art Database

Test Logic for Computer Attachment Cards

IP.com Disclosure Number: IPCOM000043740D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Baker, RG: AUTHOR [+3]

Abstract

The illustrated circuit arrangement facilitates the testing of I/O attachments to personal computer-type systems. Sets of latches added to the I/O controller attachment cards and gating paths between the latches and the computer system bus permit the computer system to obtain latched readings of address and data signals appearing on the card for diagnostic evaluation. As distinct from the conventional diagnostic technique of exercising the card and reading its signals in synchronism with operations of diagnostic programming facilities in the computer system, the present latching technique allows the attachment subsystem to capture the test information and present it to the computer system asynchronously.

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Test Logic for Computer Attachment Cards

The illustrated circuit arrangement facilitates the testing of I/O attachments to personal computer-type systems. Sets of latches added to the I/O controller attachment cards and gating paths between the latches and the computer system bus permit the computer system to obtain latched readings of address and data signals appearing on the card for diagnostic evaluation. As distinct from the conventional diagnostic technique of exercising the card and reading its signals in synchronism with operations of diagnostic programming facilities in the computer system, the present latching technique allows the attachment subsystem to capture the test information and present it to the computer system asynchronously. The advantage of this is that the testing of all associated lines can be accomplished rapidly and during standard operation without loading full diagnostic programs. To test these lines requires only four CPU cycles (one to load, and one to read each of the latches back), which is a minor subroutine that could be contained in any program and easily invoked upon error to verify the circuits. Fig. 1 illustrates the concept and highlights key elements. Two eight-bit latches 10 and 11 (e.g., type 74LS374) are used to capture memory address bit signals A0-A15 corresponding to signals appearing transiently and in parallel at the address port of the system bus (not shown), and an eight-bit latch 12 (e.g., type 74LS374) is used to capture data bit signals D0-D7 corresponding to data signals appearing on the system bus. Logic circuits 13 control the gating of address information into latches 10 and 11, and decoding logic chip modules 14 and 15 (e.g., types 74LS138 and 74LS155, as shown) control the gating of data functions into and out of latch 12. The attachment card is hard-wired to recognize particular code combinations of low-order address bits A0-A9 as commands to read or write relative to the system bus ports. As shown in Fig. 2 with respect to the card illustrated in Fig. 1, hexadecimal value "210" would command a transfer to or from the bus data port (and values "211" and "212" would, respectively, command high- and low-order transfers from the address latches to the data port) when appropria...