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Method of Delay Testing for VLSI Chips, Modules or Cards That Are Designed Using LSSD Design Rules

IP.com Disclosure Number: IPCOM000043744D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

A technique is described whereby Large-Scale Integration (LSI) and Very Large-Scale Integration (VLSI) semiconductor chips, that are designed using Level Sensitive Scan Design (LSSD) design rules, can be tested for AC performance by detecting slow performing chips. At present, it is difficult to test VLSI parts for AC characteristics except in an actual system environment. AC performance problems are often intermittent and difficult to detect. Testing is often performed on a one at a time event to detect failed parts. In the design of LSSD chips, modules and cards, latch configurations are restricted to those Shift Register Latch (SRL) circuits similar to Fig. 1.

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Method of Delay Testing for VLSI Chips, Modules or Cards That Are Designed Using LSSD Design Rules

A technique is described whereby Large-Scale Integration (LSI) and Very Large-Scale Integration (VLSI) semiconductor chips, that are designed using Level Sensitive Scan Design (LSSD) design rules, can be tested for AC performance by detecting slow performing chips. At present, it is difficult to test VLSI parts for AC characteristics except in an actual system environment. AC performance problems are often intermittent and difficult to detect. Testing is often performed on a one at a time event to detect failed parts. In the design of LSSD chips, modules and cards, latch configurations are restricted to those Shift Register Latch (SRL) circuits similar to Fig. 1. When clocks A and B are active and clock C is inactive, a data flush condition exists in that changes applied at the Scan Input of the SRL will be reflected at the Scan Output. It is typical in VLSI design to have several hundred SRLs connected together in a single scan path. Therefore, several thousand or more individual circuits may be in series between module Scan Input and Scan Output pins. It can be shown that a one-nanosecond change in each individual circuit delay would cause a one-microsecond change in the scan delay. The technique developed utilizes a long scan path to characterize and measure the delay at the chip, module or card level.

Tests for slow performing chips are tested on a standard DC t...