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Attaching a Direct Memory Device to a Single Chip Microprocessor Using an Internal or an External Random-Access Memory

IP.com Disclosure Number: IPCOM000043748D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Hudson, GA: AUTHOR

Abstract

A technique is described whereby a peripheral device requiring Direct Memory Access (DMA) activity, with either internal or external Random-Access Memory (RAM), may be attached to a single-chip microprocessor having a no hold request input, such as an Intel 8051. Fig. 1 shows the attachment of the peripheral device requiring DMA activity with the internal RAM interconnected to the microprocessor. The two-channel DMA device requests an interrupt input 1 to the microprocessor. This signal is also attached to an on-chip counter input 2. The counters serve as terminal count registers for the respective channels. They are software preloaded with a value corresponding to the maximum number of DMA cycles required for the respective channels. Each successive DMA cycle increments the counter until an overflow occurs.

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Attaching a Direct Memory Device to a Single Chip Microprocessor Using an Internal or an External Random-Access Memory

A technique is described whereby a peripheral device requiring Direct Memory Access (DMA) activity, with either internal or external Random-Access Memory (RAM), may be attached to a single-chip microprocessor having a no hold request input, such as an Intel 8051. Fig. 1 shows the attachment of the peripheral device requiring DMA activity with the internal RAM interconnected to the microprocessor. The two-channel DMA device requests an interrupt input 1 to the microprocessor. This signal is also attached to an on-chip counter input 2. The counters serve as terminal count registers for the respective channels. They are software preloaded with a value corresponding to the maximum number of DMA cycles required for the respective channels. Each successive DMA cycle increments the counter until an overflow occurs. An interrupt is then generated which has a higher priority than the DMA request interrupt. The counter interrupt routing will process the terminal count state and could include activating a DMA done signal 3 on an output port 4. The DMA request routine will use a preloaded address pointer to access the internal RAM and a preassigned high-order address to access the device, as well as activate the appropriate DMA acknowledge signal 5. This interrupt routine enables data to be moved between the peripheral device and the internal RAM. Fig. 2 sho...