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High Speed Programmable Clock Generator

IP.com Disclosure Number: IPCOM000043753D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Koennecker, OH: AUTHOR

Abstract

This programmable clock employs a free-running counter 10 that does not have to be reset, thereby allowing the clock generator to operate at higher frequencies than are possible in clock generators where such resetting occurs. A binary number representative of the desired clock frequency is entered into offset register 14. This number is transmitted to the output of latch 12 where it is compared by comparator 16 with the count of the counter 10, which driven in free-running mode by crystal oscillator 18. When the compare occurs, the comparator generates a compare pulse which functions as the clock generator output. This compare pulse is also fed back to the reset terminal of register 12, changing the number stored in the register to the output of adder 20.

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High Speed Programmable Clock Generator

This programmable clock employs a free-running counter 10 that does not have to be reset, thereby allowing the clock generator to operate at higher frequencies than are possible in clock generators where such resetting occurs. A binary number representative of the desired clock frequency is entered into offset register 14. This number is transmitted to the output of latch 12 where it is compared by comparator 16 with the count of the counter 10, which driven in free-running mode by crystal oscillator 18. When the compare occurs, the comparator generates a compare pulse which functions as the clock generator output. This compare pulse is also fed back to the reset terminal of register 12, changing the number stored in the register to the output of adder 20. The output of the adder is the sum of what is stored in registers 12 and 14. To be specific, if the latch 14 was initially loaded with the number five, the comparator 16 would produce a compare pulse when the count in the counter reached five, causing the count in the latch to be changed to ten, which is the sum of what is stored in latches 12 and 14. Another output pulse would then be produced when the counter reached the count of ten, resetting latch 12 again. Therefore, the counter would be continually changing the contents of the latch 12 which would increase increments equal to the offset, causing the comparator 16 to produce pulses each time the count in the counter...