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Metallization Scheme for Integrated Circuits

IP.com Disclosure Number: IPCOM000043794D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

The metallization scheme described in this article provides a patterned first level metallization that is "self-contacting" to silicon at any desired location. The metal-to-silicon contact widths are automatically equal to the metal width itself. All contacts including Schottky anodes and emitters thus receive full metal coverage in a compact manner. It is significant that the described scheme allows a pair of "self-contacts" to be located, wherever desired, at a distance between them which is even smaller than the photolithographic resolution. The process is as follows: 1. Form an approximately 1.2 mm thick layer 8 of an insulator, e.g., SiO2, through chemical vapor deposition (CVD)over the typical SiO2 4/Si3N4 6 passivation of a processed silicon substrate 2. Then form a 0.

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Metallization Scheme for Integrated Circuits

The metallization scheme described in this article provides a patterned first level metallization that is "self-contacting" to silicon at any desired location. The metal-to-silicon contact widths are automatically equal to the metal width itself. All contacts including Schottky anodes and emitters thus receive full metal coverage in a compact manner. It is significant that the described scheme allows a pair of "self-contacts" to be located, wherever desired, at a distance between them which is even smaller than the photolithographic resolution. The process is as follows: 1. Form an approximately 1.2 mm thick layer 8 of an insulator, e.g., SiO2, through chemical vapor

deposition (CVD)over the typical SiO2 4/Si3N4 6

passivation of a processed silicon substrate 2.

Then form a 0.4 mm layer of polysilicon 10 above

the SiO2 layer 8. Through photolithography and

reactive ion etching (RIE), form patterns in the

polysilicon 10 and SiO2 layer 8, as shown in Fig.

1. 2. Using an appropriate mask of photoresist 12, etch

the exposed Si3N4 6 and SiO2 4 (Fig. 2) in the

desired "self-contact" locations, such as the ones

for the N+ emitters in the case of bipolar

integrated circuits (ICs). 3. Deposit approximately 0.1 mm polysilicon 14, which is doped N+ either in situ or through ion implant

after the deposition. Using a mask, appropriately

pattern the polysilicon 14 and suitably drive the

N+ impurity into the monocrystal silicon to form

N+ emitters 16 in the illustration of bipolar ICs

(Fig. 3). 4. Again, using an appropriate mask of photoresist

18, etch the exposed portions of SiO2 8 to a

desired controlled extent, as illustrated at 19 in

Fig. 4. Polysilicon 10, the layer above the SiO2

8, facilitates the undercutting 19 of SiO2, which

may be done by wet etching or (selective) plasma

etching. 5. The exposed "ledge" portion of polysilicon 10 (and

14, if any) is next (preferably) removed and then

the exposed Si3N4 6 and SiO2 4 are removed

selectively. The structure at this stage is as in

Fig. 5. 6. After the removal of the resist 18, a new layer of

resist 20 is co...