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Use of Design-Of-Experiments to Establish Component Tolerances for a Phase-Locked Loop Pull-In Range

IP.com Disclosure Number: IPCOM000043796D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Talkington, CM: AUTHOR

Abstract

Determining an analytical relationship among the variables in a phase-locked loop type of circuit -- essential for establishing tolerances of key components -- has been difficult because of the complexity involved, and conventional modeling approaches have been inadequate. This invention entails usage of a design-of-experiments model employing linear regression techniques to enable the necessary analysis of circuit performance and the determination of tolerance levels. A phase-locked loop, illustrated in Fig. 1, is a complex type of circuit used in a large-screen word-processor display to generate the horizontal pulses which drive the horizontal sweep synchronized with the horizontal sweep input frequency. In the example studied, the input sync frequency is 50.

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Use of Design-Of-Experiments to Establish Component Tolerances for a Phase-Locked Loop Pull-In Range

Determining an analytical relationship among the variables in a phase-locked loop type of circuit -- essential for establishing tolerances of key components -- has been difficult because of the complexity involved, and conventional modeling approaches have been inadequate. This invention entails usage of a design-of-experiments model employing linear regression techniques to enable the necessary analysis of circuit performance and the determination of tolerance levels. A phase-locked loop, illustrated in Fig. 1, is a complex type of circuit used in a large-screen word-processor display to generate the horizontal pulses which drive the horizontal sweep synchronized with the horizontal sweep input frequency. In the example studied, the input sync frequency is 50.4 KHz, and the components are selected so that the free-running frequency of the average loop in production, given component tolerances, is 52.23 KHz. This can be calculated, along with the distribution of free-running frequencies, because the equation for the free-running frequency is known. For each circuit constructed with some combination of component tolerances, there exists an upper pull-in frequency (fH) and a lower pull-in frequency (fL). The loop will not pull in to the lock condition if a sync signal above fH or below fL is applied. Fig. 2 illustrates the distribution associated with this situation. Obviously, fH will be greater than the sync frequency in this example because the average free-running frequency is higher than the sync frequency. The problem is to prove that when units are manufactured with given component tolerances, fL will be less than the horizontal sync frequency (50.4 KHz in this example), and therefore the units will lock to the applied sync pulse. While it is known that fL = f(Vz, R109, R121, R102, R103, C102, R101) the analytic relationship between these variables and fL cannot be adequately determined due to the degree of...