Browse Prior Art Database

Versatile Custom Random-Access Memory With Logic Gate Array

IP.com Disclosure Number: IPCOM000043802D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Omet, D: AUTHOR

Abstract

This article relates to a circuit which gives the designer the ability to use on-chip custom random-access memories (RAMs) with performance and density advantages and which offers the facility of building different RAM versions on the same semiconductor part. The increased use of VLSI (very large-scale integration) gate array in the central processing units CPUs and controllers requires that large custom-designed RAMs be integrated on gate array logic chips.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 3

Versatile Custom Random-Access Memory With Logic Gate Array

This article relates to a circuit which gives the designer the ability to use on-chip custom random-access memories (RAMs) with performance and density advantages and which offers the facility of building different RAM versions on the same semiconductor part. The increased use of VLSI (very large-scale integration) gate array in the central processing units CPUs and controllers requires that large custom-designed RAMs be integrated on gate array logic chips. By means of the circuits shown in the drawing the following six RAM configurations are obtained from two basic 32 x 36 RAMs: 1 x 32 x 72 2 x 64 x 18

1 x 64 x 36

2 x 128 x 9

1 x 128 x 18

1 x 256 x 9 These circuits allow an additional decoding function and data-out gating to be performed. In addition, pre-wired interconnections which are different for the seven above configurations are provided. The pins which interface with the on-chip logic for the basic configuration are shown in Fig.
1. The circuit of Fig. 3 allows the WS and RW signals to be combined, in order to set the RAM in read or write mode. Current IW controls the operation mode namely, if IW = 1, the RAM is in read mode, and if IW = 0, it is in write mode. RW controls the read mode for the four bytes, and WS controls the write mode for each byte independently, if RW = 0. Fig. 4 shows an example of what has to be done to achieve a 1 x 64 x 36 configuration. First, the five ADD lines are dotted bit bit as are the 36 data-in (DI) lines and the 36 data-out (D0) lines. The RW signal is common for both basic RAMs of Fig. 1. These connections are made in fixed metal, to be as short as possible in order to minimize the AC load. Second, the different configurations are obtained by means of the write select (WS) control lines and data-out gate (DOG) lines. WS lines are used to select in which byte or bytes a write operation can be performed, and the DOG lines, if active, set a byte on the DO lines DO to the 1 state.

These two sets of control lines, WS and DOG,...