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Dynamic Address Allocation for a Multiplex Attachment to a Scanning Device

IP.com Disclosure Number: IPCOM000043804D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Baudelot, F: AUTHOR [+3]

Abstract

This article relates to a device for interfacing a multiplex link and the scanner device of a communication controller when the scanner is so designed that it receives and processes the received data and the data to be transmitted bit by bit. For a receive operation, the byte of one channel on the multiplex link of the X 22 type is deserialized into shift register SR1. This byte is loaded into the random-access memory (RAM). Every RAM address corresponds to one line address. When the scanner device scans a line, the corresponding byte is transferred from the RAM into shift register SR2. Only the first right bit is sent to the scanning device.

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Dynamic Address Allocation for a Multiplex Attachment to a Scanning Device

This article relates to a device for interfacing a multiplex link and the scanner device of a communication controller when the scanner is so designed that it receives and processes the received data and the data to be transmitted bit by bit. For a receive operation, the byte of one channel on the multiplex link of the X 22 type is deserialized into shift register SR1. This byte is loaded into the random-access memory (RAM). Every RAM address corresponds to one line address. When the scanner device scans a line, the corresponding byte is transferred from the RAM into shift register SR2. Only the first right bit is sent to the scanning device. When the line scanning is complete, this bit is sent to the scanner device and the content of register SR2 is shifted and loaded back into the RAM to wait for the next scanning of the line. A transmit operation is performed in the same way by using shift register SR2, and the RAM, to get the byte to be transmitted in shift register SR3. The RAM addresses are allocated as follows. One RAM word corresponding to one line is composed of one data byte and one control byte. 1.

Initialization operation The general reset is divided into two parts.

First, the channel counter is directly connected to the RAM address bus to initialize the RAM by scanning all addresses for resetting all the inhibit bits in such a way that all addresses are inhibited.

Second, the counter is connected to the pointer table which translates the channel numbers into the addresses used in the particular configuration of lines connected to the scanning device.

The pointer table causes the used addresses to be scanned and the inhibit bits...