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High Performance, High Density Static RAM Cell

IP.com Disclosure Number: IPCOM000043806D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Eardley, DB: AUTHOR [+3]

Abstract

The static RAM (random-access memory) cell, schematically shown in Fig. 1 and characterized by the layout of Fig. 2 (2nd poly for load and Vcc not shown), has two capacitances C1 and C2 for positive feedback coupling between the respective bit lines and cell nodes. The capacitance coupling is achieved by the layout where bit line 0 passes over the connection between T1 and T3 and bit line 1 passes over the connection between T0 and T2 . As the word line rises, the bit line voltage difference will increase very fast due to the positive feedback coupling and the positive feedback of the cross-coupled latch devices. Thus, the access time of the static RAM is reduced. Due to the positive feedback action, the cell size can be reduced by designing smaller latch and access devices to achieve higher density. Fig.

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High Performance, High Density Static RAM Cell

The static RAM (random-access memory) cell, schematically shown in Fig. 1 and characterized by the layout of Fig. 2 (2nd poly for load and Vcc not shown), has two capacitances C1 and C2 for positive feedback coupling between the respective bit lines and cell nodes. The capacitance coupling is achieved by the layout where bit line 0 passes over the connection between T1 and T3 and bit line 1 passes over the connection between T0 and T2 . As the word line rises, the bit line voltage difference will increase very fast due to the positive feedback coupling and the positive feedback of the cross-coupled latch devices. Thus, the access time of the static RAM is reduced. Due to the positive feedback action, the cell size can be reduced by designing smaller latch and access devices to achieve higher density. Fig. 3 shows another cell using the same positive feedback coupling between the bit lines and cell nodes as in Fig. 1. By using p- channel devices as the access transistors, the word line is permitted to stay high in the standby mode. The selected word line transition is from high level voltage to low level voltage (GND). The performance of this static RAM is greatly improved due to the faster fall time as compared to the rise time in an FET. This cell structure allows the load resistor to be tied to the word line.

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