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RAM BIT Line Isolation

IP.com Disclosure Number: IPCOM000043808D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Charest, TJ: AUTHOR [+3]

Abstract

This article describes an FET RAM (random-access memory) circuit which decouples array data bit lines from the sense circuitry after a READ action has been initiated to improve the READ performance. The decoupling also frees the data bit lines for a WRITE operation in the latter part of the same memory cycle to allow completion of a READ MODIFY WRITE function in one memory cycle. By the isolation of the bit lines from the bit sense lines when the sensing circuitry is activated, the capacitance load on the latter is reduced. Since the isolated bit lines retain most of their charge during the READ operation, a subsequent WRITE operation at the same address during the same RAM cycle is possible. The WRITE input devices are separated from the BIT sense lines to accomplish this added 'READ MODIFY WRITE function. Fig.

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RAM BIT Line Isolation

This article describes an FET RAM (random-access memory) circuit which decouples array data bit lines from the sense circuitry after a READ action has been initiated to improve the READ performance. The decoupling also frees the data bit lines for a WRITE operation in the latter part of the same memory cycle to allow completion of a READ MODIFY WRITE function in one memory cycle. By the isolation of the bit lines from the bit sense lines when the sensing circuitry is activated, the capacitance load on the latter is reduced. Since the isolated bit lines retain most of their charge during the READ operation, a subsequent WRITE operation at the same address during the same RAM cycle is possible. The WRITE input devices are separated from the BIT sense lines to accomplish this added 'READ MODIFY WRITE function. Fig. 1 shows one cell 10 of a RAM array. Cell 10 is used during a READ operation to initiate the discharge of one line of a pair 12, 14 of bit lines. The sense amplifier 16 located below the bit switches 18, 20 senses a small voltage shift (- W V) on one bit sense line 12 or 14 (via 12' or 14') and then provides the extra drive necessary to complete a negative-going transition and production of an output pulse at 22. As an incident to this transition, sense amplifier 16 pulls one of the portions 12' and 14' of the bit lines negatively to a completely discharged state. However, an added bit switch control 24 (Fig. 2) operates to decouple 12' and 14' from 12 and 14 via operation of switches 18 and 20 so that neither 12 nor 14 is fully discharged. Sense amplifier 16 is gated by a sense amplifier enable (SAE) pulse which, for maximum READ performance, is critically timed to occur at the smallest discernable - WV on line 12' o...