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Fail-Safe Clock Generation by Majority Logic

IP.com Disclosure Number: IPCOM000043812D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Koerner, S: AUTHOR [+2]

Abstract

For the fail-safe generation of computer clocks, any clock generator failure has to be eliminated as quickly as possible, so that the system output is not adversely affected. This means that the signal travel from the clock generator to the driver must exceed the time needed for detecting a failure and for eliminating it. This requirement is met by delay lines. Also provided is a majority logic. The figure shows the block diagram of a fail-safe clock generator circuit. An oscillator 1 feeds three clock generators 2, 3 and 4, whose outputs are connected to a control logic 5. Through respective delay lines 6 and 7, which can be produced with maximum accuracy, the outputs of clock generators 2 and 3 are connected to two drivers 8 and 9. The driver outputs are connected to an OR gate 10 which emits the clock signals.

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Fail-Safe Clock Generation by Majority Logic

For the fail-safe generation of computer clocks, any clock generator failure has to be eliminated as quickly as possible, so that the system output is not adversely affected. This means that the signal travel from the clock generator to the driver must exceed the time needed for detecting a failure and for eliminating it. This requirement is met by delay lines. Also provided is a majority logic. The figure shows the block diagram of a fail-safe clock generator circuit. An oscillator 1 feeds three clock generators 2, 3 and 4, whose outputs are connected to a control logic 5. Through respective delay lines 6 and 7, which can be produced with maximum accuracy, the outputs of clock generators 2 and 3 are connected to two drivers 8 and 9. The driver outputs are connected to an OR gate 10 which emits the clock signals. Control logic 5 has six outputs 11 to 16. In the failure- free state, clock generator 2 is connected to output 17, whereas in the case of a failure, clock generator 2 is disconnected from output 17 and clock generator 3 is connected to output 17. At the same time, a reset signal is applied by control logic 5, through line 13, to clock generator 2, synchronizing the latter. A similar procedure is adopted if clock generators 3 and 4 fail, but in this case, clock generator 2 remains connected to the output. For each failure, an additional clock check signal is generated on line 16 to indicate that a faulty functi...