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Browse Prior Art Database

Multiplexing Data Gates and I/O Orthogonally

IP.com Disclosure Number: IPCOM000043819D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Wortzman, D: AUTHOR

Abstract

A wiring/addressing arrangement is disclosed which allows memory array chips normally supplying four data bits per data word (ECC (error correcting code) word) to be used as chips supplying fewer data bits, in different data word organizations, without any substantial penalty in the necessary support logic. Memory array chips have been proposed where the data gate and data signals time share the same electrical lines. In the case where chips having multiple bit outputs controlled by respective data gates and normally providing multiple bits per ECC word are to be used to supply fewer bits per ECC word, a straightforward approach would require an excessive number of drivers and connections.

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Multiplexing Data Gates and I/O Orthogonally

A wiring/addressing arrangement is disclosed which allows memory array chips normally supplying four data bits per data word (ECC (error correcting code) word) to be used as chips supplying fewer data bits, in different data word organizations, without any substantial penalty in the necessary support logic. Memory array chips have been proposed where the data gate and data signals time share the same electrical lines. In the case where chips having multiple bit outputs controlled by respective data gates and normally providing multiple bits per ECC word are to be used to supply fewer bits per ECC word, a straightforward approach would require an excessive number of drivers and connections. The following wiring/ addressing arrangement avoids such driver and connection penalty while allowing the chips to supply two bits and one bit, respectively, in the examples given. Example 1 In order to reduce the number of drivers, a modified chip is required in addition to the standard chip. In the modified chip, each data gate line controls the data on an adjacent data gate line, as shown in Fig. 1. Thus, data gate E controls the data on F, and vice versa. The same is true with gates G and H. During Data Gate Sampling Time, either DG1 or DG2 is active (not both), and causes 2 IO/DG lines to be active.

Each active IO/DG line selects 2 data bits. One of these bits will use the formerly active IO/DG line, but the other will use an inactive IO/DG line, thus preventing contention on the Data Bus. Two identically modified chips can be designed to a...