Browse Prior Art Database

Dynamic RAM Dual Refresh Mechanism

IP.com Disclosure Number: IPCOM000043830D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Millas, RJ: AUTHOR [+3]

Abstract

Described is a technique to increase central processing unit (CPU) performance by reducing the time needed to refresh dynamic random-access memory (RAM). Refreshing of dynamic RAM memory usually requires either a RAM controller or a CPU coupled with a timer. The new technique described herein utilizes timers and direct memory access (DMA) channels normally found in computer systems and provides a means of refreshing RAM using only one spare DMA channel, a timer port and control logic, as shown in Fig. 1. Once the DMA 10 is initialized by a Burst Request, timer 12 starts the refresh cycle, as shown in the timing diagram in Fig. 2. At Tx time, the timer output signal is activated and is used as the DMA channel request signal.

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Dynamic RAM Dual Refresh Mechanism

Described is a technique to increase central processing unit (CPU) performance by reducing the time needed to refresh dynamic random-access memory (RAM). Refreshing of dynamic RAM memory usually requires either a RAM controller or a CPU coupled with a timer. The new technique described herein utilizes timers and direct memory access (DMA) channels normally found in computer systems and provides a means of refreshing RAM using only one spare DMA channel, a timer port and control logic, as shown in Fig. 1. Once the DMA 10 is initialized by a Burst Request, timer 12 starts the refresh cycle, as shown in the timing diagram in Fig. 2. At Tx time, the timer output signal is activated and is used as the DMA channel request signal. The DMA begins the RAM refreshing, using a dual addressing technique, performing an access from the top half of the dynamic RAM 14 to the bottom half. By using dual addressing, two refresh cycles are performed during only one DMA cycle, thereby increasing processor performance. The RAS/CAS (Row Access/Column Access) Control logic 16 provides the control required to differentiate between normal memory accessing and refresh cycles. This differentiation is accomplished by monitoring an acknowledge signal on the DMA refresh channel. When the last DMA refresh cycle is complete, DMA 10 signals timer 12 to be reinitialized, starting the refresh cycle over again.

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