Browse Prior Art Database

Multi-Master Bus Isolator

IP.com Disclosure Number: IPCOM000043833D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Johnson, WJ: AUTHOR [+4]

Abstract

A technique is described whereby a master bus isolator is positioned between the main central processing unit (CPU) of a computer system and various communication lines, so as to establish prioritization and arbitration controls. The Multi-Master Bus Isolator (MMBI) 5, as shown in Fig. 1, is positioned between the main CPU and microprocessors (MP) 1, 2, 3 and 4 for four individual communication lines. The MMBI 5 consists of six isolation and control units, as shown in Fig. 2, to provide the necessary prioritization and arbitration controls. The six units are: four Bus Isolation Logic (BIL) units 6, 7, 8 and 9; a Host Bus Isolation Logic (HBIL) unit 10; and a Priority Control Unit (PCU) 11.

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Multi-Master Bus Isolator

A technique is described whereby a master bus isolator is positioned between the main central processing unit (CPU) of a computer system and various communication lines, so as to establish prioritization and arbitration controls. The Multi-Master Bus Isolator (MMBI) 5, as shown in Fig. 1, is positioned between the main CPU and microprocessors (MP) 1, 2, 3 and 4 for four individual communication lines. The MMBI 5 consists of six isolation and control units, as shown in Fig. 2, to provide the necessary prioritization and arbitration controls. The six units are: four Bus Isolation Logic (BIL) units 6, 7, 8 and 9; a Host Bus Isolation Logic (HBIL) unit 10; and a Priority Control Unit (PCU) 11. Each BIL 6, 7, 8, and 9 contains a Data Bus Transceiver 12, Address Latches 13, and a Bus Controller 14, a Bus Arbiter 15, and Clock Support Logic 16. BILs 6, 7, 8, and 9 are activated by Bus Request Priority In (BRPN) signals on lines 18a, 18b, 18c and 18d, respectively, from the PCU 11. The HBIL 10 always has the highest priority and is controlled by the main CPU. The PCU 11, as shown in Fig. 3, is controlled by five registers 19. The first register sets the priority level for the MMBI. The second register establishes the controls for the Fixed Priority and Rotational Priority Logic Unit 20 and the Time Allocation logic Unit (TAU) 21. When time priority allocation is in effect, the third and fourth registers are used to specify the number of successi...