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Dual FIFO Dynamic RAM Manager for a Buffer Insertion Ring

IP.com Disclosure Number: IPCOM000043842D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Johnson, WJ: AUTHOR [+4]

Abstract

A technique is described to improve memory management local network architecture by utilizing dual FIFO (first-in first-out) buffers. Memory management, when used in a high-speed communications network switching architecture, such as a buffer-insertion ring-type architecture, must provide the following conditions: 1. Variable message length for received messages; 2. Track the beginning and ending addresses of variable message lengths to determine byte count; 3. Dynamically assign RAM (Random Access Memory) allocation for efficient utilization of microprocessors and I/O (Input/Output) devices; and 4. Dynamically allocate RAM segments for transmission of messages.

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Dual FIFO Dynamic RAM Manager for a Buffer Insertion Ring

A technique is described to improve memory management local network architecture by utilizing dual FIFO (first-in first-out) buffers. Memory management, when used in a high-speed communications network switching architecture, such as a buffer-insertion ring-type architecture, must provide the following conditions: 1. Variable message length for received messages; 2. Track the beginning and ending addresses of variable message lengths to determine byte count; 3. Dynamically assign RAM (Random Access Memory) allocation for efficient utilization of

microprocessors and I/O (Input/Output) devices; and 4. Dynamically allocate RAM segments for transmission of messages. In the memory management section of a buffer-insertion ring, a microprocessor 3 assigns a range of storage space using beginning and ending addresses which are loaded into a FIFO #1 buffer. The start address is then transferred from FIFO #1 to a start address incrementer 4 to speed up ring utilization and to enable an I/O device to switch to a new area in RAM 5 without waiting for a microprocessor instruction. This is particularly useful during reception of multiple messages. When the messages are received, they are stored under the control of the start address incrementer 4 and the value is pushed into FIFO #2. The microprocessor 3 determines that FIFO #2 contains the ending address of a message. Since the microprocessor 3 assigned the beginning a...