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Segmentation Register Buffering for Improved Memory Access

IP.com Disclosure Number: IPCOM000043844D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Parker, TE: AUTHOR

Abstract

A technique is described whereby the overhead of accessing segmentation registers is minimized for each translated main memory cycle for an IBM Series/1 processor. The concept is based on the empirically verifiable assumption that for a given type of main storage access, using the Instruction Space Key (ISK), Operand One Key (OP1K), Operand Two Key (OP2K), or Direct Memory Access (DMA), there is a high probability that the segmentation register used is the same segmentation register that was used for the previous storage access. At each access of the IBM Series/1 main storage, when the translator is enabled, fetching from separate segmentation registers is required as part of the overhead of the main storage cycle.

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Segmentation Register Buffering for Improved Memory Access

A technique is described whereby the overhead of accessing segmentation registers is minimized for each translated main memory cycle for an IBM Series/1 processor. The concept is based on the empirically verifiable assumption that for a given type of main storage access, using the Instruction Space Key (ISK), Operand One Key (OP1K), Operand Two Key (OP2K), or Direct Memory Access (DMA), there is a high probability that the segmentation register used is the same segmentation register that was used for the previous storage access. At each access of the IBM Series/1 main storage, when the translator is enabled, fetching from separate segmentation registers is required as part of the overhead of the main storage cycle. In some implementations, the number and/or size of the segmentation registers increases to a point that using high speed storage to store segmentation registers is not economical. To reduce this overhead, the concept, as shown in the drawing, shows how the translated main storage address on bus 10 is obtained based on receiving the selected address key and untranslated address bits 0-4 on bus 12 and the type of cycle indicator signal ISK 16, OP1K 18, OP2K 20 or DMA 22. If the selected key and high-order address bits on bus 12 match those saved in the particular one of the segmentation register buffers 30, 32, 34 and 36 for the cycle type in progress, and if the segmentation register buffer data...