Browse Prior Art Database

Attachment of Slow RAM or Peripheral to a Single-Chip Microcomputer Without Ready Line

IP.com Disclosure Number: IPCOM000043848D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Hudson, GA: AUTHOR [+2]

Abstract

A technique is described to allow slow external devices to be attached to single-chip microprocessors which have no ready line. In order to insure the integrity of data being transferred, microprocessor chips which contain no ready line, such as the Intel 8048/8051, must somehow use a ready signal from the external device. To accomplish this, a hardware state generator 1, as shown in the figure, is used to emulate the microprocessor's bus cycle, but synchronized to the ready signal of the external device. Whenever an address assigned to the external device is present on the address bus, a bus request signal 2 activates the state generator 1.

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Attachment of Slow RAM or Peripheral to a Single-Chip Microcomputer Without Ready Line

A technique is described to allow slow external devices to be attached to single- chip microprocessors which have no ready line. In order to insure the integrity of data being transferred, microprocessor chips which contain no ready line, such as the Intel 8048/8051, must somehow use a ready signal from the external device. To accomplish this, a hardware state generator 1, as shown in the figure, is used to emulate the microprocessor's bus cycle, but synchronized to the ready signal of the external device. Whenever an address assigned to the external device is present on the address bus, a bus request signal 2 activates the state generator 1. Since the generator uses the same bus timings as the processor, it will enable the high-order address clock signal 3, disable the address 4, enable data onto the address data bus 5 and activate the read or write signal. At this time, the state generator is halted until the ready signal of the device is activated. Upon activation, the generator 1 will deactivate the read or write signal and latch the external data bus (read only) by means of data latch 6, disable the data bus (write only) by means of data latch 7 and reset its internal circuitry. The microprocessor continues internal processing, since it is isolated from the bus of the external device. This concept may be adapted to work with peripheral equipment or random-access memories (...