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Densely Arrayed EPROM Having Low-Voltage Write and Erase

IP.com Disclosure Number: IPCOM000043851D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Adler, E: AUTHOR

Abstract

This erasable EPROM (electrically programmable read-only memory) has an array of FET memory cells of the two-device NOR circuit type in which both writing and erasing functions are accomplished by means of a polysilicon floating-gate tunnel-effect technology that uses low power and eliminates many diffusion coupling areas which otherwise would limit cell density rather severely in this type of array. Fig. 1 shows the type of circuitry used in this array. Each memory cell is a two-device NOR circuit containing a floating-gate FET associated with an access FET, as indicated. The figure shows four of these cells arranged respectively at the crossings of two bit lines B10 and BL1 with two word lines, each word line comprising a control gate line CG0 or CG1 and an associated read select line S10 or SL1.

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Densely Arrayed EPROM Having Low-Voltage Write and Erase

This erasable EPROM (electrically programmable read-only memory) has an array of FET memory cells of the two-device NOR circuit type in which both writing and erasing functions are accomplished by means of a polysilicon floating-gate tunnel-effect technology that uses low power and eliminates many diffusion coupling areas which otherwise would limit cell density rather severely in this type of array. Fig. 1 shows the type of circuitry used in this array. Each memory cell is a two-device NOR circuit containing a floating-gate FET associated with an access FET, as indicated. The figure shows four of these cells arranged respectively at the crossings of two bit lines B10 and BL1 with two word lines, each word line comprising a control gate line CG0 or CG1 and an associated read select line S10 or SL1. The floating-gate FETs are positioned at the respective crossings of the CG lines with the BL lines, as shown more clearly in Fig. 2, which is a sectional view through a memory cell taken along a bit line. The access FETs are at the crossings between the SL and BL lines. Referring more particularly to Fig. 2, the two devices of each memory cell are situated on an isolated P-well region in a lightly doped n-type wafer substrate. A floating gate (FG) of polycrystalline silicon (poly-1) is deposited upon a thin silicon oxide layer covering the P well in an area lying between the n+ drain and source diffusions of the floating-gate FET. Each floating gate is individual to a particular FG device. The floating gate is covered by a tunnel oxide layer of polysilicon oxide, on which is positioned a control gate (CG) line (poly-2) that is common to all of the floating-gate FETs in the same word line. The tunneling property of the polysilicon oxide layer can be enhanced by special processing techniques such as roughening the poly-1 gate and doping the polysilicon oxide with silicon. The associated access device for this memory cell has a polysilicon gate which is part of the select line (SL) common to the access devices of the same word line, this gate being positioned between diffusions, one of which is a ground line common to the respective word line, and the other of which is a combination drain-source diffusion shared by the two FETs of that memory cell. Overlying all of the memory cell structure is a metal bit line (BL) which is in insulated relationship to all parts of the memory cell structure except the drain diffusion of the floating- gate FET, to which it has an ohmic contact. The coupled drain diffusion also serves as the drain electrode of a floating-gate FET in the adjacent memory cell, if there is one. It should be noted that this is the only point of contact between the memory cell and any of the drive lines which serve it. The very small number of metal-semiconductor contacts in this type of array enables it to have a high memory cell density. To condition the memory array for...