Browse Prior Art Database

Dynamic FIFO RAM Manager for a Buffer Insertion Ring

IP.com Disclosure Number: IPCOM000043852D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Johnson, WJ: AUTHOR [+4]

Abstract

A technique is described to provide efficient memory management and improve ring utilization in ring-type local communications network architectures. Memory management, when used in a high-speed network switching architecture, such as a buffer insertion ring, must provide the following conditions: 1. Variable message length for received messages; 2. Track the beginning and ending addresses of variable message lengths to determine byte count; 3. Dynamically assign RAM (random-access memory) allocation for efficient utilization of microprocessors and I/O (input/output) devices; and 4. Dynamically allocate RAM segments for transmission of messages.

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Dynamic FIFO RAM Manager for a Buffer Insertion Ring

A technique is described to provide efficient memory management and improve ring utilization in ring-type local communications network architectures. Memory management, when used in a high-speed network switching architecture, such as a buffer insertion ring, must provide the following conditions: 1. Variable message length for received messages; 2. Track the beginning and ending addresses of variable message lengths to determine byte count; 3. Dynamically assign RAM (random-access memory) allocation for efficient utilization of

microprocessors and I/O (input/output) devices; and 4. Dynamically allocate RAM segments for transmission of messages. To accomplish the four conditions in an efficient manner, the microprocessor assigns a range of RAM space by loading the beginning address value into the Initialize Start Address Buffer 2 and the ending address value into Initialize End Address Buffer 3. The beginning address is then transferred to the Start Address Incrementer 4 and the ending address to the End Address Register 5. Buffers 2 and 3 may now be loaded with a second range of addresses. When the first message is completely received, the value in the Start Address Incrementer 4 is transferred to the first position of the FIFO (first-in, first-out) buffer 6. Since the microprocessor assigned the beginning address, it can now obtain the ending address of the first message. An algorithm in the microcode determi...