Browse Prior Art Database

Circuit for a Self-Gating Timing Chain in a Semiconductor Memory

IP.com Disclosure Number: IPCOM000043857D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Baier, E: AUTHOR [+3]

Abstract

A scheme and a circuit arrangement are described for a self-gating timing chain in a semiconductor memory, which provide for the internal row array select (RAS) phase to be used to start an enabled column array select (CAS) timing chain. Present semiconductor memories, particularly FET (field-effect transistor) memories, use select schemes with several select phases that have to be timed very carefully. Faulty timing, however slight, may lead to memory chip failure. To remedy this, an interlocking RAS/CAS scheme is described that eliminates critical timing edges in semiconductor memory address systems. Particularly in dynamic memories, the addresses are often multiplexed between the rows and columns. This necessitates that address switching be effected between RAS and CAS signals. Fig.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Circuit for a Self-Gating Timing Chain in a Semiconductor Memory

A scheme and a circuit arrangement are described for a self-gating timing chain in a semiconductor memory, which provide for the internal row array select (RAS) phase to be used to start an enabled column array select (CAS) timing chain. Present semiconductor memories, particularly FET (field-effect transistor) memories, use select schemes with several select phases that have to be timed very carefully. Faulty timing, however slight, may lead to memory chip failure. To remedy this, an interlocking RAS/CAS scheme is described that eliminates critical timing edges in semiconductor memory address systems. Particularly in dynamic memories, the addresses are often multiplexed between the rows and columns. This necessitates that address switching be effected between RAS and CAS signals. Fig. 1 is a basic circuit diagram of the RAS/CAS timing chain circuit, showing the use of interlocking as a means to avoid timing constraints. Two functions are protected against chip malfunctions: RAS/CAS interaction during address generation, data interaction: the RAS chain amplifies data by latch setting, and the CAS chain opens the bit switch and controls the data flow to the data-out circuit. The operation of the scheme is described with reference to the timing diagram of Fig. 2. An internal RAS phase is used to start an enabled CAS timing chain. If the CAS internal signal occurs too early, the bit switch (not shown)...