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Exception Handling in a Highly Overlapped Machine

IP.com Disclosure Number: IPCOM000043865D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 15K

Publishing Venue

IBM

Related People

Brantley, WC: AUTHOR [+2]

Abstract

Exceptions are difficult to handle in an overlapped machine. For example, certain machines can not define the position of the program counter at the time of an exception (imprecise interrupts). This in part is due to the floating point unit executing instructions being out of order. Highly overlapped machines will have more difficulty with exceptions. This article describes a mechanism for dealing with exceptions in highly overlapped machines. In a traditional architecture an exception causes a procedure call to occur immediately after (or in some cases before) the instruction causing the exception. This procedure call cannot be anticipated. In an overlapped machine, the I-unit may not know for some time that an exception has occurred in the E-unit.

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Exception Handling in a Highly Overlapped Machine

Exceptions are difficult to handle in an overlapped machine. For example, certain machines can not define the position of the program counter at the time of an exception (imprecise interrupts). This in part is due to the floating point unit executing instructions being out of order. Highly overlapped machines will have more difficulty with exceptions. This article describes a mechanism for dealing with exceptions in highly overlapped machines. In a traditional architecture an exception causes a procedure call to occur immediately after (or in some cases before) the instruction causing the exception. This procedure call cannot be anticipated. In an overlapped machine, the I-unit may not know for some time that an exception has occurred in the E-unit. In fact, the I-unit may have issued several instructions past the instruction causing the exception. On traditional machines, these instructions issued after the exception causing instruction must be suppressed. To suppress the execution of issued instructions complicates the design of machines. In machines which execute several instructions simultaneously, suppressing the execution of the instructions causes the dilemma: . Include the hardware necessary to "backup" to any instruction which has not finished execution (impacting cost and possibly cycle time). . Limit the degree of overlap (impacting performance). An alternative to the traditional exception architecture is necessary. Current machines allow interrupts to be ignored on a class by class basis by disabling the interrupt. If the source of the interrupt maintains its interrupt request, the interrupt will be taken when the class of interrupts is enabled by the program. In current machines, I/O interrupt requests are asserted until responded to. However, an arithmetic exception requests an interrupt for only the cycle in which the instruction appears. Thus, to be aware of an arithmetic exception, the interrupt must be enabled. The proposed system differs in that an exception never causes an interrupt. Instead, it simply sets a status bit indicating an exception occurred. Thus, the machine will never have to branch at an unexpected point in the program due to an arithmetic exception. Like the IBM System/370's scalar arithmetic, the Vector Processor (VP) causes an interrupt if any exception occurs during a vector operation, although the interrupt is not taken until the instruction finishes. VP is similar to the proposed invention in that notification of the exception is delayed. But, VP is different in that the notification is in the form of an interrupt, rather than simply setting a bit that can be tested by the program. Each source of an exception should set a bit in a status word as the event occurs. The exception status bits are "sticky", i.e., they are the logical OR of the last setting and the outcome of the current operation. The bits are only reset by the poll operation. Th...