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Circuit for Measuring KIPS

IP.com Disclosure Number: IPCOM000043879D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Lloyd, RP: AUTHOR [+3]

Abstract

This article describes a circuit for enabling the measurement of a central processing unit (CPU) through-put in kilo-instructions per second (KIPS) without degrading system performance. The circuit utilizes two high resolution and broad width binary coded decimal (BCD) accumulators which are used to measure two parameters: CPU busy and instruction count. Once obtained, the instruction count divided by CPU busy duration in seconds provides the systems KIPS rate. This measurement is a performance criterion used widely in the evaluation of computer systems. Referring to the drawing, the CPU busy measurement is obtained by connecting appropriate hardware points in the CPU under test (CPUT) via probes to customized CPU busy decode logic 3 that generates a gating signal + Enable Busy Counter.

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Circuit for Measuring KIPS

This article describes a circuit for enabling the measurement of a central processing unit (CPU) through-put in kilo-instructions per second (KIPS) without degrading system performance. The circuit utilizes two high resolution and broad width binary coded decimal (BCD) accumulators which are used to measure two parameters: CPU busy and instruction count. Once obtained, the instruction count divided by CPU busy duration in seconds provides the systems KIPS rate. This measurement is a performance criterion used widely in the evaluation of computer systems. Referring to the drawing, the CPU busy measurement is obtained by connecting appropriate hardware points in the CPU under test (CPUT) via probes to customized CPU busy decode logic 3 that generates a gating signal + Enable Busy Counter. The probe points and decode logic vary depending on the system being tested and are not described in detail. + Enable Busy Counter, when active, indicates that the CPUT is executing an instruction; when inactive, the CPUT is in an idle or wait state. + Enable Busy Counter gates the output of a programmable high frequency digital oscillator 4 to the count input of the CPU busy time accumulator 1. This accumulator measures the total time the CPUT is executing instructions. The time resolution is based on the frequency of the oscillator 4. The higher the frequency, the smaller is the total time period measured. Therefore, by programming the oscillator 4, the CPU busy time accumulator can measure elapsed time from seconds to minutes based on its width. The instruction count measurement is obtained by connecting appropriate hardware points in the CPUT via probes to customized instruction count decode logic 5 that generates a pulse called + Instruction Pulse. The probe points and decode logic vary depending on the system being tested and are not described in detail. + I...