Browse Prior Art Database

Write Improvement Scheme for Harper Cell in Low Power Supplies

IP.com Disclosure Number: IPCOM000043899D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Wang, WY: AUTHOR

Abstract

The circuit schematic shown above illustrates a write improvement scheme for a low power memory using a Harper cell which utilizes a switched bit write current to ensure fast and reliable read and write operation. This technique contrasts with the prior art where equal current sources (IREAD) are conventionally connected to both left(L) and right(R) bit lines, the same value of current serving both read and write cycles. In the scheme here disclosed, a current switch circuit switches more current(IWRITE) into one side of the bit line pair in order to speed up the fall time of the bit line voltage, thereby decreasing the time to write the Harper cell to opposite data polarity. When the Harper cell is selected, write operation is initiated from read/write control and data input circuits.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 73% of the total text.

Page 1 of 2

Write Improvement Scheme for Harper Cell in Low Power Supplies

The circuit schematic shown above illustrates a write improvement scheme for a low power memory using a Harper cell which utilizes a switched bit write current to ensure fast and reliable read and write operation. This technique contrasts with the prior art where equal current sources (IREAD) are conventionally connected to both left(L) and right(R) bit lines, the same value of current serving both read and write cycles. In the scheme here disclosed, a current switch circuit switches more current(IWRITE) into one side of the bit line pair in order to speed up the fall time of the bit line voltage, thereby decreasing the time to write the Harper cell to opposite data polarity. When the Harper cell is selected, write operation is initiated from read/write control and data input circuits. Meanwhile, the switched bit write current control is activated from read/write control. Initially, the high level voltage on the write transistor will turn off the I/O on-transistor before writing. The low cell node then starts to rise as the bit line of the I/O on- transistor side rises. The high cell node will continue to rise, due to collector-base capacitive coupling, until the low cell node crosses the SAR (sense amplifier reference) voltage, at which point the bit write current of the I/O on-transistor equals the read current. This low current ensures the fast turn-off of the I/O on- transistor. Simultaneously, th...