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X-State FET Simulation From Boolean Equations

IP.com Disclosure Number: IPCOM000043903D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Ditlow, GS: AUTHOR [+3]

Abstract

It is important to have an X-state simulation capability when simulating large scale FET circuits. Given that the logic equations exist for a circuit, we want to look up the output state of a node. If the input pattern has an X-state, then there exists the possibility of many output states. For example, consider a super buffer with two inputs (a,b) and output c, as shown in Fig. 1. When (a,b)=(X,0) there are two cases to consider: (a,b)=(1,0) and (0,0). For (1,0) the output c is clearly true. But the (0,0) case is only true if the previous value of c were true. If the previous value of c were false, then the next state of c would be false as well. Since the two cases can yield either a true or a false, we force the final state of node c to the unknown X-state.

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X-State FET Simulation From Boolean Equations

It is important to have an X-state simulation capability when simulating large scale FET circuits. Given that the logic equations exist for a circuit, we want to look up the output state of a node.

If the input pattern has an X-state, then there exists the possibility of many output states. For example, consider a super buffer with two inputs (a,b) and output c, as shown in Fig. 1. When (a,b)=(X,0) there are two cases to consider: (a,b)=(1,0) and (0,0). For (1,0) the output c is clearly true. But the (0,0) case is only true if the previous value of c were true. If the previous value of c were false, then the next state of c would be false as well. Since the two cases can yield either a true or a false, we force the final state of node c to the unknown X-state. The following procedure yields the correct results including an X-state: (1) Intersect the input pattern with the true, false, and error arrays for an output node. (2) Use the following table to resolve the state of the output node. true . true = true true . false = x true . error = x false . true = x E One pattern intersects the false false . false = false array, while another pattern false . error = x intersects the true array; error . true = x therefore, the output is the X-state. error . false = x error . error = x Fig. 2 illustrates another example of the process.

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