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Fault Simulation for Pass Transistor Circuits Using Logic Simulation Machines

IP.com Disclosure Number: IPCOM000043916D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

Barzilai, Z: AUTHOR [+4]

Abstract

An efficient fault simulation procedure for pass transistor circuits using logic simulation machines is described below. Existing fault models for use at the gate-equivalent level have proven to be inadequate for accurate pass transistor simulation [1,2]. The main reasons for this are the special features present in pass transistor circuits, i.e., bidirectionality, memory states and sneak paths. Another major inconvenience with gate-equivalent modelling is the lack of physical equivalence between the model and the actual circuit, therefore making it more difficult to evaluate significant faults. On the other hand, accurate, circuit level simulation (e.g., SPICE [3]) is too costly and time consuming. Based on the ideas presented in [4], i.e.

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Fault Simulation for Pass Transistor Circuits Using Logic Simulation Machines

An efficient fault simulation procedure for pass transistor circuits using logic simulation machines is described below. Existing fault models for use at the gate-equivalent level have proven to be inadequate for accurate pass transistor simulation [1,2]. The main reasons for this are the special features present in pass transistor circuits, i.e., bidirectionality, memory states and sneak paths.

Another major inconvenience with gate-equivalent modelling is the lack of physical equivalence between the model and the actual circuit, therefore making it more difficult to evaluate significant faults. On the other hand, accurate, circuit level simulation (e.g., SPICE [3]) is too costly and time consuming. Based on the ideas presented in [4], i.e., direct modelling of circuits at the "logic switch" level using instructions running on a logic simulation machine, appropriate fault insertion mechanisms, and efficient ways to use machines, like the YSE (Yorktown Simulation Engine) [5], for accurate fault simulation are described herein. As presented in [4], the simulation process consists of two-phased iterations: a transistor update phase and a node update phase. During the transistor update phase, those nodes which control transistor gates are used to determine whether each transistor is open or closed.

This is achieved by a single Logic Processor (LP) instruction for each transistor, using as input the node state. It is this instruction which must be modified so the transistor may appear to be stuck-open or stuck-closed. In the YSE environment [5], the above procedure can be easily performed by using the DeMorgan fields in the LP instruction. For example, a stuck-closed transistor would result from a constant one output, regardless of the input (gate node state) to the instruction. Other faults, such as classical stuck-at-one and stuck-at-zero, for both inputs and outputs, can be easily inserted as well. The procedure is similar to the one for transistors, the difference being that the instructions being modified are those which implement the node update phase. Here again, the DeMorgan fields are used to insert the desired faults. Great flexibility is available within this simulation scheme, so that a wide variety of stuck-at-faults may be simulated. For example, an input line may be set to three different kinds ("strengths") of logic one state (i.e., memory, pull-up or input), each representing a slightly different fault in terms of its possible effect on the circuit under simulation. Also possible is the simulation of "stuck-at-unknown" states on each individual node (see 4 for details on all representable node states and their meaning). As described above, fault insertion involves simple LP instruction modifications. We propose that this process be carried out within the YSE, and without host computer involvement. For this purpose, the YSE controller should h...