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Three-Dimensional Multilayer Ceramic Wiring Structure for Semiconductor Devices

IP.com Disclosure Number: IPCOM000043917D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Ecker, ME: AUTHOR

Abstract

This article describes a three-dimensional (3-D) multilayer ceramic (MLC) structure for effecting a substantial increase in semiconductor devices that are wirable in three dimensions using multilevel ceramic technology. Fig. 1 illustrates an exploded isometric view. An MLC substrate is modified so that solder connections may be disposed between chip sites in orthogonal rows. Strips of MLC materials are then processed to provide for mounting of semiconductor dies on both surfaces. The MLC strips are laser cut to provide notches for interlocking an array of enclosures disposed about the chip sites on the top surface of the MLC substrate. This structure, formed by the interlocked MLC strips, is then registered and reflow-attached to the orthogonal rows of solder connections on the MLC substrate.

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Three-Dimensional Multilayer Ceramic Wiring Structure for Semiconductor Devices

This article describes a three-dimensional (3-D) multilayer ceramic (MLC) structure for effecting a substantial increase in semiconductor devices that are wirable in three dimensions using multilevel ceramic technology. Fig. 1 illustrates an exploded isometric view. An MLC substrate is modified so that solder connections may be disposed between chip sites in orthogonal rows. Strips of MLC materials are then processed to provide for mounting of semiconductor dies on both surfaces. The MLC strips are laser cut to provide notches for interlocking an array of enclosures disposed about the chip sites on the top surface of the MLC substrate. This structure, formed by the interlocked MLC strips, is then registered and reflow-attached to the orthogonal rows of solder connections on the MLC substrate. These solder connections provide for the pathways in the MLC substrate to continue vertically into any of the vertically disposed orthogonally oriented MLC strips. In this manner, semiconductor chips may be reflow-attached to the surface of the MLC substrate as well as the surfaces of the orthogonally oriented MLC strips, thus effecting a considerable increase in circuit or memory device density per unit volume. The height of the orthogonally interlocked strips is only limited by the ability to satisfactorily deliver the required voltage levels, as well as provide for the wiring and I/O needs of the vertically disposed chips. Three-dimensional module groups may be configured using differing basic wiring structures in any mix; e.g., the orthogonal strips may be structured by using MCP, transverse via or Cu/INVAR*/Cu with a multiwire 3- D module. A compliant cooling means must be provided for chips disposed between modular 3-D structures. A modular cooling enhancement is required to accommodate one or more rows of chip sites as well as being able to address chips disposed vertically on opposed 3-D module walls. Fig. 2 illustrates a slotted ceramic strip (A) with array chips (B) disposed on the surface. Over the array chips is an array of compliant thermal contactors (C) joined to a common strip by cantilever spring members (E). The array of thermal contactors is configured so as to assemble over the edge of the ceramic carrier, thereby allowing thermal contactors to be located over array chips joined to both surfaces of the ceramic strip. Cantilever members (F), part of the common strip, are located at both ends and snap into the partial slot (G) for common strip retention. The common strip has extensions (H) formed so as to interloc...