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Sample Preparation Technique for Auger Analysis

IP.com Disclosure Number: IPCOM000043928D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Gajda, JJ: AUTHOR [+2]

Abstract

The Auger analysis of semiconductor device contacts is a time consuming operation involving the careful removal of many single layers of a multilayer metallic contact, e.g., PtSi, Cr-Cr2O3, AlCu, etc., in the process of examining their various metallic interfaces. The use of chemical surface etching techniques to remove the overlaying metal layers is difficult to control and can inadvertently introduce spurious contaminants into the sample chip under evaluation. The technique here described avoids the problems noted above and is employed successfully in the preparation of Auger analysis samples, providing accurate delineation of the contacts without introducing contamination or electrical charges into the specimens.

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Sample Preparation Technique for Auger Analysis

The Auger analysis of semiconductor device contacts is a time consuming operation involving the careful removal of many single layers of a multilayer metallic contact, e.g., PtSi, Cr-Cr2O3, AlCu, etc., in the process of examining their various metallic interfaces. The use of chemical surface etching techniques to remove the overlaying metal layers is difficult to control and can inadvertently introduce spurious contaminants into the sample chip under evaluation. The technique here described avoids the problems noted above and is employed successfully in the preparation of Auger analysis samples, providing accurate delineation of the contacts without introducing contamination or electrical charges into the specimens. The front side contact surfaces 12 of chip sample 10 are first subjected to an in situ sputter cleaning to remove any passivation protective layer extant. This is followed with a blanket evaporation of Al, Al-Cu, or any conducting, malleable, metal film 14 over the entire chip face, effectively shorting out all exposed contacts 18, including suspect degraded ones. This metallized chip face is then mechanically bonded against the surface of a rigid aluminum stud 16, which thereafter acts as a mechanical support for the chip 10 during subsequent analysis operations. The exposed back face of the silicon chip can now be removed by conventional mechanical polishing and plasma etch processes, exposing all cont...