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Distributed Error Checking/Correcting Scheme for Distributed Cache Memory Systems

IP.com Disclosure Number: IPCOM000043940D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Gheewala, TR: AUTHOR [+2]

Abstract

A method is provided which accomplishes single error correction and double error detection per word by using an orthogonal parity checking scheme. Row parity checking is done on the DRAM (dynamic random-access memory) chips and column parity checking is done on the memory controller chip. The idea behind distributed error checking/correction (DECC) is that the bits in the row buffer are only partially checked in the DRAM, with the remainder of the checking done via byte parity on the data words read from a memory bank consisting of nine DRAM chips. DECC distributes the parity check/generation logic between the DRAM chips 11 and a memory control chip 12. This logic is also distributed, to some extent, over time.

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Distributed Error Checking/Correcting Scheme for Distributed Cache Memory Systems

A method is provided which accomplishes single error correction and double error detection per word by using an orthogonal parity checking scheme. Row parity checking is done on the DRAM (dynamic random-access memory) chips and column parity checking is done on the memory controller chip. The idea behind distributed error checking/correction (DECC) is that the bits in the row buffer are only partially checked in the DRAM, with the remainder of the checking done via byte parity on the data words read from a memory bank consisting of nine DRAM chips. DECC distributes the parity check/generation logic between the DRAM chips 11 and a memory control chip 12. This logic is also distributed, to some extent, over time. Each row in the memory array will have N parity bits, each of which is associated with a group of R/N bits in the row, where R equals the number of bits in a row. The row parity bits 13 are generated every time a row buffer is restored to the main memory cell array of the DRAM chip 11. Column parity bit 14 is generated by the memory controller as each data byte is transmitted to the memory chips. When a memory request involves an address outside the row currently contained in the row buffers of the DRAM chips, these rows are restored to the memory cell arrays of the DRAM chips, and a new set of rows are read. At this time the row parity bits 13 for the new row are checked. If there are no row parity errors, the contents of the row are assumed to be correct and access to various bits in the row buffer is performed as usual with parity being checked on each byte (column) access. If bad parity is encountered in a byte access, either there is a driver/ receiver fault or there is a double error in a single row; either of which is detected but uncorrectable. If, on the othe...