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Circuit to Minimize Poll Capture and Poll Propagate Time Without Introducing Metastability in IBM Series/1 I/O Adapters

IP.com Disclosure Number: IPCOM000043941D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Welbon, EH: AUTHOR

Abstract

Described is a technique whereby IBM Series/1 Input/Output (I/O) feature adapter card performance is improved by minimizing poll propagation time. Any S/1 system having multiple interrupting and/or cycle stealing I/O adapter cards would benefit, since the circuit will capture or propagate the poll signal (an arbitration signal on the S/1 bus) in a minimum amount of time, without introducing metastability conditions. The primary objective of the circuit is to propagate the poll signal in one block delay time or about eight nanoseconds. At present, the propagation time over ten adapter cards requires 1,180 nanoseconds. The proposed circuit would require a maximum of only 260 nanoseconds over the ten cards, yielding a time savings of 920 nanoseconds.

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Circuit to Minimize Poll Capture and Poll Propagate Time Without Introducing Metastability in IBM Series/1 I/O Adapters

Described is a technique whereby IBM Series/1 Input/Output (I/O) feature adapter card performance is improved by minimizing poll propagation time. Any S/1 system having multiple interrupting and/or cycle stealing I/O adapter cards would benefit, since the circuit will capture or propagate the poll signal (an arbitration signal on the S/1 bus) in a minimum amount of time, without introducing metastability conditions. The primary objective of the circuit is to propagate the poll signal in one block delay time or about eight nanoseconds. At present, the propagation time over ten adapter cards requires 1,180 nanoseconds. The proposed circuit would require a maximum of only 260 nanoseconds over the ten cards, yielding a time savings of 920 nanoseconds. Using the design specifications as defined for S/1 I/O attachment cards, the circuit takes advantage of two factors: 1. There is a 180 ns skew time from poll ID valid to poll active (as measured at the channel output). 2. There is a 100 ns skew time from poll ID quiescent to poll ID active (as measured at channel output), and that poll ID is valid until either poll return or poll burst return becomes active. The basic poll propagate function, as shown in the figure, requires that initially poll ID 1 (+poll 0, 3 & 4) be at its quiescent value. Only after 100 ns of quiescence may the poll ID 1 change to an active value. While the poll ID 1 is quiescent, multiplexer 2 has a negative value at its output M3. This value is inverted by inverter 3, enabling latches 4 to be in a transparent (flushing) mode....