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Fet Ram Chip Double Density Scheme

IP.com Disclosure Number: IPCOM000043942D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR

Abstract

Using two chip select (CS) inputs, instead of one CS and one store address register (SAR) input, allows either running double dense chips without module power or input difference penalties or a half-good program with no AC power penalty. Replacing two chips in a module with one double dense chip does not require module input differences. Also, another SAR input is not required since the high-order SAR is generated directly from the two chip selects. There will be no net power increase. Also, this scheme allows a half-good program for a chip design with no AC power dissipation penalty. Only one of the two half-good chips will dissipate AC power. As shown in the figure, each chip has two chip select inputs, CS1 and CS2.

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Fet Ram Chip Double Density Scheme

Using two chip select (CS) inputs, instead of one CS and one store address register (SAR) input, allows either running double dense chips without module power or input difference penalties or a half-good program with no AC power penalty. Replacing two chips in a module with one double dense chip does not require module input differences. Also, another SAR input is not required since the high-order SAR is generated directly from the two chip selects. There will be no net power increase. Also, this scheme allows a half-good program for a chip design with no AC power dissipation penalty. Only one of the two half-good chips will dissipate AC power. As shown in the figure, each chip has two chip select inputs, CS1 and CS2. A Start signal will be generated and the chip will start when either one or the other goes to its selected level state (down level for negative select, which will be used in this example) and the other stays at its unselected level state. The proper SAR output will be generated. A separate SAR input is not needed. Start circuit 10 must be modified to start with one of two inputs CS1 or CS2 going to an active level and not both.

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