Browse Prior Art Database

Low Power Level Shifter

IP.com Disclosure Number: IPCOM000043958D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Houghton, RJ: AUTHOR

Abstract

The power dissipation problem that arises when shifting signals from higher to lower voltage while maintaining minimum circuit delay is solved with a circuit having a transition-sensitive current source which "powers up" only during the switching of the PNP current switch. The transition-sensitive current source assumes that the circuit shown in Fig. 1 is in a condition with T6 conducting prior to switching. A change in input causes emitter follower driver T5 to pull the base of PNP T6 to positive. Because of the high stored charge in this slow PNP, node A is caused to rise, as shown in the timing diagram (Fig. 2). The rising potential of node A charges the feedback capacitor CF through the base of current source T9. This charge is multiplied by the b of T9 and greatly increases Ip.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Low Power Level Shifter

The power dissipation problem that arises when shifting signals from higher to lower voltage while maintaining minimum circuit delay is solved with a circuit having a transition-sensitive current source which "powers up" only during the switching of the PNP current switch. The transition-sensitive current source assumes that the circuit shown in Fig. 1 is in a condition with T6 conducting prior to switching. A change in input causes emitter follower driver T5 to pull the base of PNP T6 to positive. Because of the high stored charge in this slow PNP, node A is caused to rise, as shown in the timing diagram (Fig. 2). The rising potential of node A charges the feedback capacitor CF through the base of current source T9. This charge is multiplied by the b of T9 and greatly increases Ip. Ip flows through T3 of the current switch to drive the base of PNP T7. This high level of Ip causes a fast transfer of charge from T6 to T7. When T7 turns on, node A returns to its original level and current source T9 returns to its "idling" current. Therefore, a lower circuit power is achieved by means of this transition-sensitive current source that only "powers up" during circuit switching.

1

Page 2 of 2

2

[This page contains 1 picture or other non-text object]