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Shorthand Notation for I-Shadow Target Addresses

IP.com Disclosure Number: IPCOM000043972D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+4]

Abstract

An I-Shadow of 2K entries can form its target addresses by using internal pointers to other I-Shadow entries rather than full addresses. The pointers are maintained and established as in a normal I-Shadow with the exception that lines pointed to are made MRU at prefetch time. This reduces the possibility that when an entry is LRUed from the I-Shadow, other entries still point to it. With larger caches, erroneous prefetching is reduced since the newly entered lines within the I-Shadow will remain in the cache longer. Currently, with 128 B-lines and 31-bit addressing, a standard 2K entry I-Shadow devotes 6 KB for target addresses. This shorthand reduces this to 3 KB. A mechanism for lookup based on location and return based on address is required with this shorthand. The pointer approach takes an additional cycle.

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Shorthand Notation for I-Shadow Target Addresses

An I-Shadow of 2K entries can form its target addresses by using internal pointers to other I-Shadow entries rather than full addresses. The pointers are maintained and established as in a normal I-Shadow with the exception that lines pointed to are made MRU at prefetch time. This reduces the possibility that when an entry is LRUed from the I-Shadow, other entries still point to it. With larger caches, erroneous prefetching is reduced since the newly entered lines within the I-Shadow will remain in the cache longer. Currently, with 128 B-lines and 31-bit addressing, a standard 2K entry I-Shadow devotes 6 KB for target addresses. This shorthand reduces this to 3 KB. A mechanism for lookup based on location and return based on address is required with this shorthand. The pointer approach takes an additional cycle.

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