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Shadow Structure to Perform D-Line Prefetching

IP.com Disclosure Number: IPCOM000043975D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+4]

Abstract

Consider a shadow structure defined as follows: The first level (FROM) is a directory-like structure containing unique entries arranged into congruence classes and the second level contains two associated addresses. The first of these two addresses extends the key associated with the first level, and the second address is the address of the prefetch D-Line (Data-Line). The second level is further extended to include a six-bit count field. Consider two of the above structures called SI and SD. The directory level of SI will contain the addresses in the directory of a comparably sized I-Cache (say, 2000 entries) (64 congruence classes-32 way set associative). The directory level of SD will contain the addresses in the directory of a comparably sized D-Cache (Data-Cache).

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Shadow Structure to Perform D-Line Prefetching

Consider a shadow structure defined as follows: The first level (FROM) is a directory-like structure containing unique entries arranged into congruence classes and the second level contains two associated addresses. The first of these two addresses extends the key associated with the first level, and the second address is the address of the prefetch D-Line (Data-Line). The second level is further extended to include a six-bit count field. Consider two of the above structures called SI and SD. The directory level of SI will contain the addresses in the directory of a comparably sized I-Cache (say, 2000 entries) (64 congruence classes-32 way set associative). The directory level of SD will contain the addresses in the directory of a comparably sized D-Cache (Data-Cache). The remainder of the discussion deals with: (1) How entries are made in the second levels initially. (2) How the count field is maintained. (3) How entries are overwritten in the second level. (1) For any access to SIO+SD the following procedure is followed: The current I accesses SI The current D accesses SD The access to SI returns a putative D-Miss address (or null) and a count (6-Bit field). The access to SD returns a putative I-Miss address (or null) and a count. On the triggering event (D-miss) nulls will be found in SI/SD. If either SI/SD or both contain nulls, an entry C is made with: (I,D,M) relationship instantiated and the count field is set...