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Time-Multiplexed Bus for Interconnecting Multiple Microprocessor Cards to Each Other and to a Common Set of Peripherals and Memory

IP.com Disclosure Number: IPCOM000044023D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR

Abstract

This article describes a method of connecting multiple microprocessor cards on a common bus so that they may interface with each other and to a common set of input/output (I/O) devices on the bus virtually at the same time without the connection problem usually encountered in such systems and without degrading performance of any processor significantly. Connecting multiple microprocessor cards on a common bus so that they may interface with each other and to a common set of I/O devices on the bus has been done in the past by using a number of different arbitration schemes which allowed one card at a time to control the bus, thus forcing others to wait when more than one processor wanted to control the bus in a given period of time.

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Time-Multiplexed Bus for Interconnecting Multiple Microprocessor Cards to Each Other and to a Common Set of Peripherals and Memory

This article describes a method of connecting multiple microprocessor cards on a common bus so that they may interface with each other and to a common set of input/output (I/O) devices on the bus virtually at the same time without the connection problem usually encountered in such systems and without degrading performance of any processor significantly. Connecting multiple microprocessor cards on a common bus so that they may interface with each other and to a common set of I/O devices on the bus has been done in the past by using a number of different arbitration schemes which allowed one card at a time to control the bus, thus forcing others to wait when more than one processor wanted to control the bus in a given period of time. This arbitration process can significantly degrade system performance when the processors involved required a number of I/O operations. In order to avoid this performance degradation, the method disclosed herein provides a means of forming multiple logical busses on the same physical bus, all of which can be active simultaneously without contention. Fig. 1 is a diagram of a multiplexed I/O bus illustrating this concept. It should be noted that the five virtual I/O busses shown are actually time multiplexed on a single physical bus, and are shown separately only to clarify the potential function of the system. The result is that multiple I/O processor (IOP) cards can have access over the same physical bus to a common set of feature cards or I/O devices without contention. Every feature card can be attached to any or all of the virtual busses in the system under program control. Fig. 1 shows one of the cards (Feature 5) attached to two virtual busses simultaneously. In order to understand how this is possible, we must first examine the standard microprocessor bus cycle of the devices to be used. Fig. 2A is based on a typical Motorola 68000 microprocessor bus cycle. However, other microprocessors have similar cycles and could use the same concept. Looking first at what happens with the address and data lines, the first part of the bus cycle is used by...