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LSSD Clock Insertion Method for Reducing Test Time

IP.com Disclosure Number: IPCOM000044054D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Bouldin, EA: AUTHOR [+2]

Abstract

Level sensitive scan design (LSSD) tests (called tester loops) are normally comprised of five or more actions where each action consists of one or more stimulus patterns. This standard LSSD format, as shown in the flow chart, may be selectively altered by a process of pattern insertion, i.e., by adding patterns to the body of the tester loops. Clock insertion is a special case of pattern insertion characterized by adding patterns which are generally LSSD clock pairs (e.g., A-clock/B-clock, or C-clock/B-clock). The clock-insertion method modifies selected test sequences from an existing test set to improve their fault detection efficiency, thereby making it possible to completely eliminate other test sequences. The clock-insertion method begins with an analysis step that determines the number of faults caught in each tester loop.

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LSSD Clock Insertion Method for Reducing Test Time

Level sensitive scan design (LSSD) tests (called tester loops) are normally comprised of five or more actions where each action consists of one or more stimulus patterns. This standard LSSD format, as shown in the flow chart, may be selectively altered by a process of pattern insertion, i.e., by adding patterns to the body of the tester loops. Clock insertion is a special case of pattern insertion characterized by adding patterns which are generally LSSD clock pairs (e.g., A- clock/B-clock, or C-clock/B-clock). The clock-insertion method modifies selected test sequences from an existing test set to improve their fault detection efficiency, thereby making it possible to completely eliminate other test sequences. The clock-insertion method begins with an analysis step that determines the number of faults caught in each tester loop. The analysis distinguishes the number of faults caught by measuring primary outputs (PO) and the number of faults caught by measuring shift register latches (SRL). These two types of faults will be subsequently referred to as P-faults and S-faults, respectively. The success of the insertion method is based on adding patterns that do not mask faults already caught by the original tester loop. If a tester loop catches only P-faults, then the last action in the tester loop (which can only catch S-faults) is not contributing to the test coverage. LSSD clock sequences can be added to the tester loop immediatel...