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Interfacing of Slow Direct Memory Access and Peripheral Devices to a High Speed Bus

IP.com Disclosure Number: IPCOM000044056D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR

Abstract

This article describes an arrangement for allowing a direct memory access (DMA) controller on an input/output (I/O) card to take control of the local bus on that card before taking over the main interconnecting bus between cards. This improves bus performance by avoiding wait states and idle time on the main bus. Many microprocessor peripheral chips work somewhat slower than the microprocessor which controls them. As a result, when read and write operations address these chips (either under microprocessor or DMA control), wait states must be added in the bus cycle to slow it down to the speed of the peripheral chip. Depending on system configuration, throughput can be significantly reduced by these wait states.

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Interfacing of Slow Direct Memory Access and Peripheral Devices to a High Speed Bus

This article describes an arrangement for allowing a direct memory access (DMA) controller on an input/output (I/O) card to take control of the local bus on that card before taking over the main interconnecting bus between cards. This improves bus performance by avoiding wait states and idle time on the main bus. Many microprocessor peripheral chips work somewhat slower than the microprocessor which controls them. As a result, when read and write operations address these chips (either under microprocessor or DMA control), wait states must be added in the bus cycle to slow it down to the speed of the peripheral chip. Depending on system configuration, throughput can be significantly reduced by these wait states. Adding to this problem, some DMA controllers allow the bus to remain idle for a complete bus cycle time before actually taking control of the bus, thus potentially decreasing bus throughput by a factor of two. The system disclosed herein is illustrated in the block diagram of the drawing. It allows a DMA controller 13 on an I/O card 14 to take control of the local busses 10, 11 and 12 on that card without taking over the main interconnecting busses 15, 16 and 17 between cards. As soon as an I/O device 18 requests DMA service, the DMA controller 13 requests and is granted control (artificially) of the local busses 10, 11 and 12. Its lines are buffered by gate 19 and control logic 20 from the I/O devices 18 requiring service, so that if the processor 21 initiates a bus cycle accessing the local bus, the DMA lines are isolated from the bus by degating the DMA lines, and the DMA cycle is extended by holding a not ready or not data transfer acknowledge condition on the DMA controller. When the processor has finished its cycle, the DMA lines are gated onto the local bus again and access to the device needing service begins again. It should be noted that the DMA controller 13 does not have to start over gaining control of the bus; it thinks it never lost control of the bus but is just waiting for an extra-slow device to respond. Also, it should be noted that DMA cycles on a specific local bus are only affected by processor access to that local bus, but are not affected by processor access to other local busses on other cards in the system. For a DMA transfer from the I/O card 14 to memory 27 on the processor card 22 or a memory card (not shown) attached to the main bus, the data from the local de...