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Microcoded DSP Channel Subsystem

IP.com Disclosure Number: IPCOM000044072D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bolan, JE: AUTHOR

Abstract

A current processor has channels that are integrated with the instruction processing unit (IPU), and uses a trap mechanism to cycle steal from the IPU to accomplish the channel's various functions. A Microcoded Dual Stream Processor (DSP) channel subsystem is essentially two of these uniprocessors (UPs) coupled together with additional logic to allow the IPUs to communicate with each other and with a complex storage interface, to permit the sharing of one main storage (BSM (Basic Storage Module)). The DSP channel design is made up of two physically separate I/O engines that function independently.

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Microcoded DSP Channel Subsystem

A current processor has channels that are integrated with the instruction processing unit (IPU), and uses a trap mechanism to cycle steal from the IPU to accomplish the channel's various functions. A Microcoded Dual Stream Processor (DSP) channel subsystem is essentially two of these uniprocessors (UPs) coupled together with additional logic to allow the IPUs to communicate with each other and with a complex storage interface, to permit the sharing of one main storage (BSM (Basic Storage Module)). The DSP channel design is made up of two physically separate I/O engines that function independently. This type of channel configuration has very little impact when the machine is functioning in IBM System/370 mode but poses a new and complex microcode design when the machine must function in S370XA mode, since the I/O must appear to have no affinity to a CPU and any CPU can issue I/O requests to any I/O device in the system. To accomplish the above, the design needs the following: 1. A process to communicate from one IPU to another. This is accomplished by a hardware broadcast internal interrupt and a storage communication area. This mechanism is utilized by both the IPU for certain instructions and by the channel for almost all the S370XA channel subsystem instructions. 2. A technique of determining if a given I/O device has possible channel paths on any of the two CPUs. This is designed for every subchannel in the subchannel control b...